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NB100LVEP221FAG Datasheet

  • NB100LVEP221FAG

  • 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver

  • 165.93KB

  • 11頁

  • ONSEMI

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NB100LVEP221
2.5V/3.3V 1:20 Differential
HSTL/ECL/PECL Clock Driver
Description
The NB100LVEP221 is a low skew 1鈭抰o鈭?0 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The two clock inputs are differential
ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The
LVPECL input signals can be either differential configuration or
single鈭抏nded (if the V
BB
output is used).
The LVEP221 specifically guarantees low output鈭抰o鈭抩utput skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure tightest skew, both sides of differential outputs should be
terminated identically into 50
W
even if only one output is being used.
If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
The NB100LVEP221, as with most other ECL devices, can be
operated from a positive V
CC
supply in LVPECL mode. This allows the
LVEP221 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies. For more information on PECL terminations, designers should
refer to Application Note AND8020/D.
The V
BB
pin, an internally generated voltage supply, is available to this
device only. For single鈭抏nded LVPECL input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and
V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
should be left open.
Single鈭抏nded CLK input operation is limited to a V
CC
鈮?/div>
3.0 V in
LVPECL mode, or V
EE
鈮?/div>
鈭?.0
V in NECL mode.
Features
http://onsemi.com
MARKING
DIAGRAM*
NB100
LVEP221
AWLYYWWG
LQFP鈭?2
FA SUFFIX
CASE 848H
A
WL
YY
WW
G
52
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
15 ps Typical Output鈭抰o鈭扥utput Skew
40 ps Typical Device鈭抰o鈭扗evice Skew
Jitter Less than 2 ps RMS
Maximum Frequency > 1.0 GHz Typical
Thermally Enhanced 52鈭扡ead LQFP
V
BB
Output
540 ps Typical Propagation Delay
LVPECL and HSTL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V
EE
= 0 V
NECL Mode Operating Range:
V
CC
= 0 V with V
EE
=
鈭?.375
V to
鈭?.8
V
Q Output will Default Low with Inputs Open or at V
EE
Pin Compatible with Motorola MC100EP221
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 7
1
Publication Order Number:
NB100LVEP221/D

NB100LVEP221FAG 產(chǎn)品屬性

  • 160

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器

  • 100LVEP

  • 扇出緩沖器（分配），多路復(fù)用器

  • 1

  • 2:20

  • 是/是

  • ECL，HSTL，LVPECL

  • ECL，PECL

  • 1GHz

  • 2.375 V ~ 3.8 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 52-LQFP 裸露焊盤

  • 52-LQFP（10x10）

  • 托盤

  • NB100LVEP221FAGOS

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