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NB100LVEP17 Datasheet

  • NB100LVEP17

  • 2.5V / 3.3V Quad Differential Driver/Receiver

  • 147.59KB

  • 10頁

  • ONSEMI

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NB100LVEP17
2.5V / 3.3V Quad Differential
Driver/Receiver
Description
The NB100LVEP17 is a 4-bit differential line receiver. The design
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device.
Features
http://onsemi.com
MARKING
DIAGRAMS*
N100
VP17
ALYWG
G
TSSOP鈭?0
DT SUFFIX
CASE 948E
24
1
24
1
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
250 ps Typical Propagation Delay
Low Profile QFN Package
PECL Mode Operating Range: V
CC
= 2.375 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
鈭?.375
V to
鈭?.8
V
Q Output Will Default LOW with Inputs Open or at V
EE
V
BB
Output
Pb鈭扚ree Packages are Available
24 PIN QFN
MN SUFFIX
CASE 485L
A
L
Y
W
G
N100
VP17
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 7
1
Publication Order Number:
NB100LVEP17/D

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