NB100EP223
3.3V 1:22 Differential
HSTL/PECL to HSTL Clock
Driver with LVTTL Clock
Select and Output Enable
Description
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MARKING
DIAGRAM*
The NB100EP223 is a low skew 1鈭抰o鈭?2 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
differential HSTL or LVPECL and they are selected by the CLK_SEL
pin which is LVTTL. To avoid generation of a runt clock pulse when
the device is enabled/disabled, the Output Enable (OE), which is
LVTTL, is synchronous ensuring the outputs will only be
enabled/disabled when they are already in LOW state (See Figure 7).
The NB100EP223 guarantees low output鈭抰o鈭抩utput skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output pair, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to 鈥渞educe power and switching noise as much as
possible.鈥?Any unused single line of a differential pair should be
terminated the same as the used line to maintain balanced loads on the
differential driver outputs. The output structure uses an open emitter
architecture and will be terminated with 50
W
to ground instead of a
standard HSTL configuration (See Figure 6). The wide VIHCMR
specification allows both pair of CLOCK inputs to accept LVDS
levels.
Features
LQFP鈭?4
FA SUFFIX
CASE 848G
A
WL
YY
WW
G
NB100
EP223
AWLYYWWG
64
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb鈭扚ree Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
鈥?/div>
100 ps Typical Device鈭抰o鈭扗evice Skew
鈥?/div>
25 ps Typical Within Device Skew
鈥?/div>
HSTL Compatible Outputs Drive 50
W
to Ground With No
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Offset Voltage
Maximum Frequency >500 MHz
1 ns Typical Propagation Delay
LVPECL and HSTL Mode Operating Range: V
CC
= 3 V to 3.6 V
with GND = 0 V, V
CCO
= 1.6 V to 2.0 V
Q Output will Default Low with Inputs Open
Thermally Enhanced 64鈭扡ead LQFP
CLOCK Inputs are LVDS鈭扖ompatible; Requires External 100
W
LVDS Termination Resistor
Pb鈭扚ree Packages are Available*
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
November, 2006
鈭?/div>
Rev. 7
1
Publication Order Number:
NB100EP223/D
NB100EP223FA 產品屬性
160
集成電路 (IC)
時鐘/計時 - 時鐘緩沖器，驅動器
100EP
扇出緩沖器（分配），多路復用器
1
2:22
是/是
HSTL，LVDS，LVPECL
HSTL
500MHz
3 V ~ 3.6 V
0°C ~ 85°C
表面貼裝
64-LQFP 裸露焊盤
64-LQFP（10x10）
托盤
NB100EP223FAOS
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