鈥?/div>
Both outputs are 3-State for further multiplexer expansion
DESCRIPTION
The 74F251A is a logic implementation of a single 8-position switch
with the switch position controlled by the state of three Select (S0,
S1, S2) inputs. True (Y) and complementary (Y) outputs are both
provided. The output enable (OE) is active Low. When OE is High,
both outputs are in High impedance state, allowing multiple output
connections to a common bus without driving nor loading the bus
significantly. All but one device must be in High impedance state to
avoid high currents that would exceed the maximum ratings when
the outputs of the 3-State devices are tied together. When the output
of more than one device is tied together the user must ensure that
there is no overlap in the active Low portion of the output enable
voltages.
PIN CONFIGURATION
I3
I2
I1
I0
Y
Y
OE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
I4
I5
I6
I7
S0
S1
S2
SF00778
TYPE
74F251A
TYPICAL
PROPAGATION
DELAY
4.5ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
19mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
鹵10%,
T
amb
= 0擄C to +70擄C
N74F251AN
N74F251AD
PKG
DWG #
SOT38-4
SOT162-1
16-pin plastic DIP
16-pin plastic SO
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
I0鈥揑7
S0鈥揝2
OE
Y, Y
Data inputs
Select inputs
Output Enable input (active Low)
Data outputs
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40
LOAD VALUE HIGH/LOW
20碌A/0.6mA
20碌A/0.6mA
20碌A/0.6mA
3mA/24mA
NOTE:
One (1.0) FAST unit load is defined as: 20碌A in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
4
3
2
1
15
14
13
12
IEC/IEEE SYMBOL
7
11
10
I0
I1
I2
I3
I4
I5
I6
I7
9
4
3
2
1
6
0
G
2
0
7
5
MUX
EN
11
10
9
7
S0
S1
S2
OE
Y
Y
15
14
13
V
CC
= Pin 16
GND = Pin 8
5
6
12
SF00779
SF00780
1996 Jan 05
1
853鈥?358 16191
1
2
3
4
5
