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MX28F2100BTC-90 Datasheet

  • MX28F2100BTC-90

  • 2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY

  • 45頁

  • MCNIX

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PRELIMINARY
MX28F2100B
2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY
FEATURES
鈥?262,144x8/131,072x16 switchable
鈥?Fast access time: 70/90/120ns
鈥?Low power consumption
鈥?50mA maximum active current
鈥?100uA maximum standby current
鈥?Programming and erasing voltage 12V
鹵
7%
鈥?Command register architecture
鈥?Byte/Word Programming (50 us typical)
鈥?Auto chip erase 5 sec typical
(including preprogramming time)
鈥?Block Erase (Any one from 5 blocks:16K-Byte x1,
8K-Byte x2, 96K-Byte x1, and 128K-Byte x1)
鈥?Auto Erase with Erase Suspend capability
鈥?Status Register feature for Device status detection
鈥?Auto Erase (chip & block) and Auto Program
鈥?Status Registers
鈥?10,000 minimum erase/program cycles
鈥?Latch-up protected to 100mA from -1 to VCC+1V
鈥?Package type:
鈥?44-pin SOP
鈥?48-pin TSOP (Type 1)
GENERAL DESCRIPTION
The MX28F2100B is a 2-mega bit Flash memory or-
ganized as 256K bytes of 8 bits or 128K words of 16
bits switchable. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-
volatile random access memory. The MX28F2100B
is packaged in 44-pin SOP and 48-pin TSOP(I). It is
designed to be reprogrammed and erased in-system
or in-standard EPROM programmers.
The standard MX28F2100B offers access times as
fast as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX28F2100B has separate chip
enable (CE) and output enable (OE ) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX28F2100B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs and
fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling.
The
MX28F2100B uses a 12.0V
鹵
7% VPP supply to
perform the High Reliability Erase and auto Program/
Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
BLOCK STRUCTURE
A16~A0
1FFFFH
128 K-BYTE BLOCK
10000H
0FFFFH
96 K-BYTE BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
00000H
Word Mode (x16) Memor y Map
*Byte Mode operation should include
A-1(LSB) for addressing
8 K-BYTE BLOCK
8 K-BYTE BLOCK
16 K-BYTE BLOCK
P/N: PM0382
1
REV. 1.5, MAR. 24, 1998

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