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MX28F128J3TBC-15 Datasheet

  • MX28F128J3TBC-15

  • EEPROM

  • 6頁

  • ETC

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BRIEF
MX28F128J3
128M [x8/x16] SINGLE 3V PAGE MODE FLASH MEMORY
FEATURES
鈥?2.7V to 3.6V operation voltage
鈥?Block Structure
- 128 x 128Kbyte Erase Blocks
鈥?Fast random / page mode access time
- 150/25 ns Read Access Time
鈥?128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
鈥?32-Byte Write Buffer
- 6 us/byte Effective Programming Time
鈥?Enhanced Data Protection Features Absolute Protec-
tion with VPEN = GND
- Flexible Block Locking
- Block Erase/Program Lockout during Power Transi-
tions
Software Feature
鈥?Support Common Flash Interface (CFI)
- Flash device parameters stored on the device and
provide the host system to access.
鈥?Automation Suspend Options
- Block Erase Suspend to Read
- Block Erase Suspend to Program
- Program Suspend to Read
Hardware Feature(Not for 48-TSOP/48-RTSOP)
鈥?A0 pin
- Select low byte address when device is in byte mode.
Not used in word mode.
鈥?STS pin
- Indicates the status of the internal state machine.
鈥?VPEN pin
- For Erase /Program/ Block Lock enable.
鈥?VCCQ Pin
- The output buffer power supply, control the device 's
output voltage.
Performance
鈥?Low power dissipation
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
- Deep power-down current: 5uA
鈥?High Performance
- Block erase time: 2s typ.
- Byte programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
鈥?Program/Erase Endurance cycles: 10,000 cycles
Packaging
- 48-Lead TSOP
- 48-Lead RTSOP
- 56-Lead TSOP
- 64-ball CSP
Technology
- MX28F128J3 using Nbit (0.25u) Flash Technology
OCT/30/2002
1

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