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MX28F1000PPC-12C4 Datasheet

  • MX28F1000PPC-12C4

  • 1M-BIT [128K x 8] CMOS FLASH MEMORY

  • 33頁

  • MCNIX

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MX28F1000P
1M-BIT [128K x 8] CMOS FLASH MEMORY
FEATURES
鈥?131,072 bytes by 8-bit organization
鈥?Fast access time: 70ns(Vcc:5V鹵5%; CL:35pF)
90/120ns(Vcc:5V鹵10%; CL:100pF)
鈥?Low power consumption
鈥?50mA maximum active current
鈥?100uA maximum standby current
鈥?Programming and erasing voltage 12V
鹵
5%
鈥?Command register architecture
鈥?Byte Programming (15us typical)
鈥?Auto chip erase 5 seconds typical
(including preprogramming time)
鈥?Block Erase
鈥?Optimized high density blocked architecture
鈥?Four 4-KB blocks
鈥?/div>
鈥?Seven 16-KB blocks
Auto Erase (chip & block) and Auto Program
鈥?DATA polling
鈥?Toggle bit
10,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Advanced CMOS Flash memory technology
Compatible with JEDEC-standard byte-wide 32-pin
EPROM pinouts
Package type:
鈥?32-pin plastic DIP
鈥?32-pin PLCC
鈥?32-pin TSOP (Type 1)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
GENERAL DESCRIPTION
The MX28F1000P is a 1-mega bit Flash memory or-
ganized as 128K bytes of 8 bits each. MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX28F1000P is packaged in 32-pin PDIP, PLCC
and TSOP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM program-
mers.
The standard MX28F1000P offers access times as
fast as 70 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate
bus contention, the MX28F1000P has separate chip
enable (CE) and output enable (OE ) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX28F1000P uses a command
register to manage this functionality, while
maintaining a standard 32-pin pinout. The
command register allows for 100% TTL level control
inputs and fixed power supply levels during erase
and programming, while maintaining maximum
EPROM compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling.
The
MX28F1000P uses a 12.0V
鹵
5% VPP supply to
perform the Auto Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
P/N: PM0340
1
REV. 1.6,JAN. 19, 1999

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