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MX23C4096PC-15 Datasheet

  • MX23C4096PC-15

  • 4M-BIT [256K x 16] CMOS MASK ROM

  • 6頁(yè)

  • ETC

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INDEX
MX23C4096
4M-BIT [256K x 16] CMOS MASK ROM
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
256K x 16 organization (JEDEC pin out)
Single +5V power supply
Fast access time: 100/120/150/200ns
Totally static operation
Completely TTl compatible
鈥?Operating current: 60mA
鈥?Standby current: 100uA
鈥?Package
- 40 pin DIP (600 mil)
- 44 pin PLCC
GENERAL DESCRIPTION
The MX23C4096 is a 5V only, 4M-bit, Read Only
Memory. It is organized as 512Kx16 bit. MX23C4096
has a static standby mode, and has an access time of
100/120/150/200ns. It is designed to be compatible with
all microprocessors and similar applications in which
high performance, large bit storage and simple interfac-
ing are important design considerations.
MX23C4096 offers automatic power-down, with power-
down controlled by the chip enable (CE/CE) input. When
CE/CE is not selected, the device automatically powers
down and remains in a low-power standby mode as long
as CE/CE stays in the unselected mode.
The OE/OE inputs as well as CE/CE input may be pro-
grammed either active High or Low.
PIN CONFIGURATION
40PDIP
NC
CE/CE
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
VSS
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OE/OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
BLOCK DIAGRAM
CE/CE
OE/OE
CONTROL
LOGIC
OUTPUT
BUFFERS
Q0~Q15
MX23C4096
.
.
A0~A17
ADDRESS
INPUTS
.
.
.
.
.
.
Y-DECODER
X-DECODER
.
.
.
.
.
.
.
.
Y-DECODER
4M BIT
ROM
ARRAY
VCC
VSS
CE/CE
VCC
44 PLCC
Q13
Q14
Q15
6
PIN DESCRIPTION
A17
A16
A15
A14
40
39
A13
A12
A11
A10
A9
NC
NC
Q12
Q11
Q10
Q9
Q8
VSS
NC
Q7
Q6
Q5
Q4
7
1 44
12
MX23C4096
34
VSS
NC
A8
A7
A6
Symbol
A0~A17
Q0~Q15
CE/CE
OE/OE
VCC
VSS
Pin Function
Address Inputs
Data Outputs
Chip Enable Input
Output Enable Input
Power Supply Pin (+5V)
Ground Pin
17
18
23
29
28
A5
Q3
Q2
Q1
Q0
OE/OE
A0
A1
A2
A3
P/N:PM0257
NC
A4
REV. 1.3, OCT. 08, 1996
1

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