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MX23C2100PC-15 Datasheet

  • MX23C2100PC-15

  • 2M-BIT 256K x 8/128K x 16 CMOS MASK ROM

  • 7頁

  • MCNIX

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INDEX
MX23C2100
2M-BIT [256K x 8/128K x 16] CMOS MASK ROM
FEATURES
鈥?Switchable organization
- 256K x 8 (byte mode)
- 128K x 16 (word mode)
鈥?Single +5V power supply
鈥?Fast access time:150/200ns
鈥?Totally static operation
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Completely TTL compatible
Operating current: 60mA
Standby current: 100uA
Package type:
- 40 pin DIP (600 mil)
GENERAL DESCRIPTION
The MX23C2100 is a 5V only, 2M-bit, Read Only
Memory. It is organized as 256K x 8 bits (byte mode) or
as 128K x 16 bit (word mode) depending on BYTE (pin
31) voltage level. MX23C2100 has a static standby
mode, and has an access time of 150/200ns. It is de-
signed to be compatible with all microprocessors and
similar applications in which high performance, large bit
storage and simple interfacing are important design con-
siderations.
MX23C2100 offers automatic power-down, with power-
down controlled by the chip enable (CE/CE) input. When
CE/CE is not selected, the device automatically powers
down and remains in a low-power standby mode as long
as CE/CE stays in the unselected mode.
The OE/OE inputs as well as CE/CE input may be pro-
grammed either active High or Low.
PIN CONFIGURATION
40 PDIP
NC
A7
A6
A5
A4
A3
A2
A1
A0
CE/CE
VSS
OE/OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
BLOCK DIAGRAM
CE/CE
OE/OE
BYTE
Q15/A-1
CONTROL
LOGIC
OUTPUT
BUFFERS
Q0~Q14
.
A0~A16
ADDRESS
INPUTS
.
.
.
.
.
.
.
VCC
VSS
Y-DECODER
.
.
.
.
.
.
.
.
Y-DECODER
MX23C2100
X-DECODER
2M BIT
ROM ARRAY
PIN DESCRIPTION
Symbol
A0~A16
Q0~Q14
CE/CE
OE/OE
BYTE
Q15/A-1
VCC
VSS
Pin Function
Address Input
Data Output
Chip Enable Input
Output Enable Input
Word/Byte Selection
Q15 (Word mode)/LSB addr. (Byte
mode)
Power Supply Pin (+5V)
Ground Pin
REV. 2.2, JAN. 28, 1999
P/N:PM0134
1

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