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MUN51XXT1 Datasheet

  • MUN51XXT1

  • Bias Resistor Transistor

  • 12頁

  • ONSEMI

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MUN5111T1 Series
Preferred Devices
Bias Resistor Transistor
PNP Silicon Surface Mount Transistor
with Monolithic Bias Resistor Network
This new series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base鈭抏mitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space. The device is housed in
the SC鈭?0/SOT鈭?23 package which is designed for low power
surface mount applications.
Features
http://onsemi.com
PNP SILICON
BIAS RESISTOR
TRANSISTORS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Pb鈭扚ree Packages are Available
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
The SC鈭?0/SOT鈭?23 package can be soldered using wave or reflow.
The modified gull鈭抴inged leads absorb thermal stress during
soldering eliminating the possibility of damage to the die.
鈥?/div>
Available in 8 mm embossed tape and reel 鈭?Use the Device Number
to order the 7 inch/3000 unit reel. Replace 鈥淭1鈥?with 鈥淭3鈥?in the
Device Number to order the 13 inch/10,000 unit reel.
MAXIMUM RATINGS
(T
A
= 25擄C unless otherwise noted)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
50
50
100
Unit
Vdc
Vdc
mAdc
PIN 1
BASE
(INPUT)
R
1
R
2
PIN 3
COLLECTOR
(OUTPUT)
PIN 2
EMITTER
(GROUND)
3
1
2
SC鈭?0/SOT鈭?23
CASE 419
STYLE 3
MARKING DIAGRAM
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
6x M
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation
T
A
= 25擄C
Derate above 25擄C
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Lead
Junction and Storage Temperature Range
1. FR鈭? @ Minimum Pad
2. FR鈭? @ 1.0 x 1.0 inch Pad
Symbol
P
D
Max
202 (Note 1)
310 (Note 2)
1.6 (Note 1)
2.5 (Note 2)
618 (Note 1)
403 (Note 2)
280 (Note 1)
332 (Note 2)
鈭?5 to +150
Unit
mW
擄C/W
擄C/W
擄C/W
擄C
6x
M
= Specific Device Code
(See Order Info Table)
= Date Code
ORDERING INFORMATION
See specific ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
R
qJA
R
qJL
T
J
, T
stg
Preferred
devices are recommended choices for future use
and best overall value.
漏
Semiconductor Components Industries, LLC, 2004
1
October, 2004 鈭?Rev. 7
Publication Order Number:
MUN5111T1/D

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