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MTD20P06HDL Datasheet

  • MTD20P06HDL

  • TMOS POWER FET LOGIC LEVEL 15 AMPERES 60 VOLTS RDS(on) = 175...

  • 310.45KB

  • 12頁

  • MOTOROLA   MOTOROLA

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD20P06HDL/D
鈩?/div>
Data Sheet
HDTMOS E-FET
鈩?/div>
High Density Power FET
DPAK for Surface Mount
Designer's
MTD20P06HDL
Motorola Preferred Device
P鈥揅hannel Enhancement鈥揗ode Silicon Gate
This advanced high鈥揷ell density HDTMOS E鈥揊ET is designed to
withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a drain鈥搕o鈥搒ource
diode with a fast recovery time. Designed for low鈥搗oltage,
high鈥搒peed switching applications in power supplies, converters
and PWM motor controls, and other inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Ultra Low RDS(on), High鈥揅ell Density, HDTMOS
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Avalanche Energy Specified
Surface Mount Package Available in 16 mm, 13鈥搃nch/2500
Unit, Tape & Reel, Add T4 Suffix to Part Number
TMOS POWER FET
LOGIC LEVEL
15 AMPERES
60 VOLTS
RDS(on) = 175 M鈩?/div>
鈩?/div>
D
G
CASE 369A鈥?3, Style 2
DPAK
S
MAXIMUM RATINGS
(TC = 25擄C unless otherwise noted)
Rating
Drain鈥揝ource Voltage
Drain鈥揋ate Voltage (RGS = 1.0 M鈩?
Gate鈥揝ource Voltage 鈥?Continuous
Gate鈥揝ource Voltage
鈥?Non鈥揜epetitive (tp
鈮?/div>
10 ms)
Drain Current 鈥?Continuous
Drain Current
鈥?Continuous @ 100擄C
Drain Current
鈥?Single Pulse (tp
鈮?/div>
10
碌s)
Total Power Dissipation
Derate above 25擄C
Total Power Dissipation @ TC = 25擄C (1)
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?Starting TJ = 25擄C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 15 Apk, L = 2.7 mH, RG = 25
鈩?
Thermal Resistance 鈥?Junction to Case
Thermal Resistance
鈥?Junction to Ambient
Thermal Resistance
鈥?Junction to Ambient (1)
Maximum Temperature for Soldering Purposes, 1/8鈥?from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer鈥檚 Data for 鈥淲orst Case鈥?Conditions
鈥?The Designer鈥檚 Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves 鈥?representing boundaries on device characteristics 鈥?are given to facilitate 鈥渨orst case鈥?design.
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
60
60
鹵
15
鹵
20
15
9.0
45
72
0.58
1.75
鈥?55 to 150
300
1.73
100
71.4
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/擄C
Watts
擄C
mJ
擄C/W
TJ, Tstg
EAS
R
胃JC
R
胃JA
R
胃JA
TL
擄C
Designer鈥檚, E鈥揊ET and HDTMOS are trademarks of Motorola Inc.
TMOS is a registered trademark of Motorola Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 1
漏
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1995
1

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