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MTD15N06V Datasheet

  • MTD15N06V

  • TMOS POWER FET 15 AMPERES 60 VOLTS

  • 221.02KB

  • 10頁

  • MOTOROLA   MOTOROLA

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MOTOROLA
Designer's
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTD15N06V/D
TMOS V
Power Field Effect Transistor
DPAK for Surface Mount
TMOS V is a new technology designed to achieve an on鈥搑esis-
tance area product about one鈥揾alf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E鈥揊ET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
鈥?/div>
On鈥搑esistance Area Product about One鈥揾alf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
鈥?/div>
Faster Switching than E鈥揊ET Predecessors
鈩?/div>
Data Sheet
MTD15N06V
Motorola Preferred Device
N鈥揅hannel Enhancement鈥揗ode Silicon Gate
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM
TM
D
G
S
CASE 369A鈥?3, Style 2
DPAK Surface Mount
Features Common to TMOS V and TMOS E鈥揊ETS
鈥?/div>
Avalanche Energy Specified
鈥?/div>
IDSS and VDS(on) Specified at Elevated Temperature
鈥?/div>
Static Parameters are the Same for both TMOS V and TMOS E鈥揊ET
鈥?/div>
Surface Mount Package Available in 16 mm 13鈥搃nch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25擄C unless otherwise noted)
Rating
Drain鈥揝ource Voltage
Drain鈥揋ate Voltage (RGS = 1.0 M鈩?
Gate鈥揝ource Voltage 鈥?Continuous
Gate鈥揝ource Voltage
鈥?Single Pulse (tp
鈮?/div>
50 ms)
Drain Current 鈥?Continuous @ 25擄C
Drain Current
鈥?Continuous @ 100擄C
Drain Current
鈥?Single Pulse (tp
鈮?/div>
10
碌s)
Total Power Dissipation @ 25擄C
Derate above 25擄C
Total Power Dissipation @ TA = 25擄C, when mounted to minimum recommended pad size
Operating and Storage Temperature Range
Single Pulse Drain鈥搕o鈥揝ource Avalanche Energy 鈥?Starting TJ = 25擄C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25
鈩?
Thermal Resistance 鈥?Junction to Case
Thermal Resistance
鈥?Junction to Ambient
Thermal Resistance
鈥?Junction to Ambient, when mounted to minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8鈥?from case for 10 seconds
Symbol
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
Value
60
60
鹵
20
鹵
25
15
8.7
45
55
0.36
2.1
鈥?55 to 175
113
2.73
100
71.4
260
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/擄C
Watts
擄C
mJ
擄C/W
TJ, Tstg
EAS
R
胃JC
R
胃JA
R
胃JA
TL
擄C
Designer鈥檚 Data for 鈥淲orst Case鈥?Conditions
鈥?The Designer鈥檚 Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves 鈥?representing boundaries on device characteristics 鈥?are given to facilitate 鈥渨orst case鈥?design.
E鈥揊ET, Designer鈥檚 and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
漏
Motorola TMOS
Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1

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