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MTD10N10ELT4 Datasheet

  • MTD10N10ELT4

  • TMOS E-FET Power Field Effect Transistor DPAK for Surface Mo...

  • 8頁(yè)

  • ONSEMI

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MTD10N10EL
TMOS E鈭扚ET鈩?/div>
Power Field Effect Transistor
DPAK for Surface Mount
N鈭扖hannel Enhancement鈭扢ode Silicon
Gate
This advanced TMOS E鈭扚ET is designed to withstand high energy
in the avalanche and commutation modes. The new energy efficient
design also offers a drain鈭抰o鈭抯ource diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
Features
V
DSS
100 V
http://onsemi.com
R
DS(ON)
TYP
0.22
鈩?/div>
I
D
MAX
10 A
N鈭扖hannel
D
鈥?/div>
Avalanche Energy Specified
鈥?/div>
Source鈭抰o鈭扗rain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
鈥?/div>
Diode is Characterized for Use in Bridge Circuits
鈥?/div>
I
DSS
and V
DS(on)
Specified at Elevated Temperature
鈥?/div>
Surface Mount Package Available in 16 mm, 13鈭抜nch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(T
C
= 25擄C unless otherwise noted)
Parameter
Drain鈭抰o鈭扴ource Voltage
Drain鈭抰o鈭扜ate Voltage (R
GS
= 1.0 M鈩?
Gate鈭抰o鈭扴ource Voltage 鈥?Continuous
鈥?Non鈭扲epetitive (t
p
鈮?/div>
10 ms)
Drain Current 鈥?Continuous
Drain Current
鈥?Continuous @ 100擄C
Drain Current
鈥?Single Pulse (t
p
鈮?/div>
10
碌s)
Total Power Dissipation @ T
C
= 25擄C
Derate above 25擄C
Total Power Dissipation @ T
A
= 25擄C (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain鈭抰o鈭扴ource Avalanche
Energy 鈥?Starting T
J
= 25擄C
(V
DD
= 25 Vdc, V
GS
= 5.0 Vdc, I
L
= 10 Apk,
L = 1.0 mH, R
G
=25
鈩?
Thermal Resistance 鈥?Junction to Case
鈥?Junction to Ambient (Note 1)
鈥?Junction to Ambient (Note 2)
Maximum Temperature for Soldering
Purposes, 1/8鈥?from case for 10 seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
Value
100
100
鹵15
鹵20
10
6.0
35
40
0.32
1.75
鈭?5 to
150
50
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/擄C
Watts
擄C
mJ
1 2
3
G
S
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
4
Drain
YWW
10N
10EL
2
1 Drain 3
Gate
Source
Shipping
鈥?/div>
75 Units/Rail
2500 Tape & Reel
DPAK
DPAK
Publication Order Number:
MTD10N10EL/D
DPAK
CASE 369C
(Surface Mount)
Style 2
10N10EL=Device Code
Y
= Year
WW
= Work Week
T
J
, T
stg
E
AS
ORDERING INFORMATION
Device
MTD10N10EL
MTD10N10ELT4
Package
R
胃JC
R
胃JA
R
胃JA
T
L
3.13
100
71.4
260
擄C/W
鈥燜or information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
擄C
1. When surface mounted to an FR4 board using minimum recommended pad size.
2. When surface mounted to an FR4 board using 0.5 sq in pad size.
漏
Semiconductor Components Industries, LLC, 2004
1
March, 2004 鈭?Rev. 1

MTD10N10ELT4 產(chǎn)品屬性

  • 2,500

  • 分離式半導(dǎo)體產(chǎn)品

  • FET - 單

  • -

  • MOSFET N 通道，金屬氧化物

  • 邏輯電平門(mén)

  • 100V

  • 10A

  • 220 毫歐 @ 5A，5V

  • 2V @ 250µA

  • 15nC @ 5V

  • 1040pF @ 25V

  • 1.75W

  • 表面貼裝

  • TO-252-3，DPak（2 引線(xiàn)+接片），SC-63

  • DPAK-3

  • 帶卷 (TR)

  • MTD10N10ELT4OSTR

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