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MT9173 Datasheet

  • MT9173

  • Digital Subscriber Interface Circuit with RxSB

  • 22頁(yè)

  • MITEL

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廬
ISO
2
-CMOS ST-BUS鈩?FAMILY
MT9173/74
Digital Subscriber Interface Circuit
with
RxSB
Digital Network Interface Circuit
with
RxSB
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Receive sync output pulse
Full duplex transmission over a single twisted
pair
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3km (9173) and 4 km (9174) loop reach
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
MITEL ST-BUS compatible
Low power (typically 50 mW), single 5V supply
ISSUE 2
March 1997
Ordering Information
MT9173AE
24 Pin Plastic DIP (300mil)
MT9173AN
24 Pin SSOP
MT9173AP
28 Pin PLCC
MT9174AE
24 Pin Plastic DIP (300 mil)
MT9174AN
24 Pin SSOP
MT9174AP
28 Pin PLCC
-40擄C to
+
85擄C
Description
The MT9173 (DSIC) and MT9174 (DNIC) are
functionally identical to the MT9171/72 except for the
addition of one feature. The MT9173/74 include a
digital output pin indicating the temporal position of
the received "SYNC" bit of the biphase transmission.
This feature is especially useful for systems such as
PCS wireless base station applications requiring
close synchronization between microcells.
The MT9173 and MT9174 are identical except for the
MT9173 having a shorter loop reach. The generic
"DNIC" will be used to reference both devices unless
otherwise noted. The MT9173/74 are fabricated in
Mitel鈥檚 ISO
2
-CMOS process.
Applications
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
T
DD
Digital PCS (DECT, CT2, PHS) base
stations requiring cell synchronization
Digital subscriber lines
High speed data transmission over twisted
wires
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
DSTi/Di
CDSTi/
CDi
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
L
OUT
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
Control
Register
Transmit
Timing
V
Bias
Address
Echo Canceller
Error
Signal
Echo Estimate
鈥?/div>
DPLL
MUX
L
OUT
DIS
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control
Sync Detect
Status
Receive
Precan
鈭?/div>
+
Receive
Filter
-1
+2
L
IN
OSC2
DSTo/Do
CDSTo/
CDo
RxSB
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
OSC1
V
DD
V
SS
V
Bias
V
Ref
Figure 1 - Functional Block Diagram
9-137

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