MT9123AE Datasheet

IC型號：
MT9123AE
PDF描述：
CMOS Dual Voice Echo Canceller
文件大?。?/label>
193.76KB
PDF頁數(shù)：
32頁
芯片廠家：
MITEL

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廬

CMOS

MT9123

Dual Voice Echo Canceller

Preliminary Information

Features

鈥?/div>

Dual channel 64ms or single channel 128ms

echo cancellation

Conforms to ITU-T G.165 requirements

Narrow-band signal detection

Programmable double-talk detection threshold

Non-linear processor with adaptive suppression

threshold and comfort noise insertion

Offset nulling of all PCM channels

Controllerless mode or Controller mode with

serial interface

ST-BUS or variable-rate SSI PCM interfaces

Selectable

碌/A-Law

ITU-T G.711;

碌/A-Law

Sign

Mag; linear 2鈥檚 complement

Per channel selectable 12 dB attenuator

Transparent data transfer and mute option

19.2 MHz master clock operation

ISSUE 1

October 1996

Ordering Information

MT9123AP

28 Pin PLCC

MT9123AE

28 Pin PDIP

-40

擄C

to + 85

擄C

Description

The MT9123 Voice Echo Canceller implements a

cost effective solution for telephony voice-band echo

cancellation

conforming

ITU-T

G.165

requirements. The MT9123 architecture contains two

echo cancellers which can be con鏗乬ured to provide

dual channel 64 millisecond echo cancellation or

single channel 128 millisecond echo cancellation.

The MT9123 operates in two major modes:

Controller or Controllerless. Controller mode allows

access to an array of features for customizing the

MT9123 operation. Controllerless mode is for

applications where default register settings are

suf鏗乧ient.

Applications

鈥?/div>

Wireless Telephony

Trunk echo cancellers

Sin

Linear/

碌/A-Law

Offset

Null

Non-Linear

Processor

Adaptive

Filter

Control

Linear/

碌/A-Law

Sout

Microprocessor

Interface

Double-Talk

Detector

Programmable

Bypass

Narrow-Band

Detector

Linear/

碌/A-Law

12dB

Attenuator

Offset

Null

Linear/

碌/A-Law

Rout

ENA2

ENB2

NLP

LAW

FORMAT

IC3

IC4

Rin

ENA1

ENB1

CONFIG1

CONFIG2

S1/DATA1

S2/DATA2

S3/CS

S4/SCLK

Echo Canceller A

Echo Canceller B

IC1

IC2

VDD

VSS

PWRDN

F0od

F0i

BCLK/C4i

MCLK

Figure 1 - Functional Block Diagram

8-45

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