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MT90871 Datasheet

  • MT90871

  • Flexible 8K Digital Switch (F8KDX)

  • 641.37KB

  • 65頁

  • ZARLINK   ZARLINK

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MT90871
Flexible 8K Digital Switch (F8KDX)
Data Sheet
Features
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8,192-channel x 8,192-channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to
form a non-blocking switching matrix with 32
stream inputs and 32 stream outputs.
4,096-channel x 4,096 channel non-blocking
Backplane to Local stream switch.
4,096-channel x 4,096 channel non-blocking
Local to Backplane stream switch.
4,096-channel x 4,096 channel non-blocking
Backplane input to Backplane output switch.
4,096-channel x 4,096 channel non-blocking
Local input to Local output stream switch.
Rate conversion on all data paths, Backplane to
Local, Local to Backplane, Backplane to
Backplane and Local to Local streams.
Backplane port accepts 16 ST-BUS streams with
data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s
or 16.384Mb/s in any combination.
Local port accepts 16 ST-BUS streams with data
rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or
16.384Mb/s, in any combination.
V
DD_IO
V
DD_CORE
December 2002
Ordering Information
MT90871AV
196 Ball LBGA
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鈥?/div>
鈥?/div>
-40C to +85C
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
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鈥?/div>
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Per-stream channel and bit delay for Local input
streams.
Per-stream channel and bit delay for Backplane
input streams.
Per-stream advancement for Local output
streams.
Per-stream advancement for Backplane output
streams.
Constant throughput delay for frame integrity.
Per-channel high impedance output control for
Local and Backplane streams.
Per-channel driven-high output control for Local
and Backplane streams.
High impedance-control outputs for external
drivers on Backplane and Local port.
RESET
鈥?/div>
鈥?/div>
V
SS (GND)
ODE
BSTi0-15
Backplane Data Memories
(4,096 channels)
Local
Interface
LSTi0-15
Backplane
Interface
BSTo0-15
BCST0-1
BORS
Backplane
Connection Memory
(4,096 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
LSTo0-15
LCST0-1
Local Data Memories
(4,096 channels)
Backplane
Timing Unit
Local
Timing
Unit
Microprocessor Interface
PLL
and Internal Registers
LORS
FP8o
FP16o
C8o
C16o
FP8i
C8i
Test Port
V
DD_PLL
DS CS R/W
A14-A0
DTA
D15-D0 TMS TDi TDo TCK
TRST
Figure 1 - MT90871 Functional Block Diagram
Zarlink Semiconductor Inc.
1

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