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MT90869AG Datasheet

  • MT90869AG

  • Flexible 16K Digital Switch (F16kDX)

  • 1264.07KB

  • 76頁

  • ZARLINK   ZARLINK

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MT90869
Flexible 16K Digital Switch (F16kDX)
Data Sheet
Features
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16,384-channel x 16,384-channel non-blocking
unidirectional switching.The Backplane and
Local inputs and outputs can be combined to
form a non-blocking switching matrix with 64
stream inputs and 64 stream outputs.
8,192-channel x 8,192-channel non-blocking
Backplane to Local stream switch.
8,192-channel x 8,192-channel non-blocking
Local to Backplane stream switch.
8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch.
8,192-channel x 8,192-channel non-blocking
Local input to Local output stream switch.
Rate conversion on all data paths, Backplane to
Local, Local to Backplane, Backplane to
Backplane and Local to Local streams.
Backplane port accepts 32 ST-BUS streams
with data rates of 2.048Mb/s, 4.096Mb/s,
8.192Mb/s or 16.384Mb/s in any combination,
or a fixed allocation of 16 streams at
32.768Mb/s.
Local port accepts 32 ST-BUS streams with
data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s
V
DD_IO
V
DD_CORE
December 2002
Ordering Information
MT90869AG
272 Ball - PBGA
-40 to +85
o
C
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or 16.384Mb/s, in any combination.
Per-stream channel and bit delay for Local input
streams.
Per-stream channel and bit delay for Backplane
input streams.
Per-stream advancement for Local output
streams.
Per-stream advancement for Backplane output
streams.
Constant throughput delay for frame integrity.
Per-channel high impedance output control for
Local and Backplane streams.
Per-channel driven-high output control for local
and backplane streams.
High impedance-control outputs for external
drivers on backplane and local port.
RESET
ODE
V
SS (GND)
BSTi0-31
Backplane Data Memories
(8,192 channels)
Local
Interface
LSTi0-31
Backplane
Interface
BSTo0-31
BCST0-3
BORS
Backplane
Connection Memory
(8,192 locations)
Local
Connection Memory
(8,192 locations)
Local
Interface
LSTo0-31
LCST0-3
Local Data Memories
(8,192 channels)
Backplane
Timing Unit
LORS
FP8i
Local
Timing
Unit
Microprocessor Interface
and Internal Registers
FP8o
FP16o
C8o
C16o
PLL
C8i
Test Port
V
DD_PLL
DS CS R/W A14-A0 DTA D15-D0
TMS TDi TDo TCK TRST
Figure 1 - MT90869 Functional Block Diagram
Zarlink Semiconductor Inc.
1

MT90869AG 產(chǎn)品屬性

  • 0現(xiàn)貨

  • 停產(chǎn)

  • -

  • 托盤

  • 停產(chǎn)

  • 開關(guān)

  • -

  • 1

  • 3V ~ 3.6V

  • 160mA

  • -

  • -40°C ~ 85°C

  • 表面貼裝型

  • 272-BGA

  • 272-PBGA（27x27）

MT90869AG相關(guān)型號(hào)PDF文件下載

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