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Description
The MT9075B is a single chip device which
integrates an advanced PCM 30 framer with a Line
Interface Unit (LIU).
The framer interfaces to a 2.048 Mbit/s backplane
and provides selectable rate data link access with
optional HDLC controllers for S
a
bits and channel 16.
The LIU interfaces the framer functions to the PCM
30 transformer-isolated four wire line.
The MT9075B meets or supports the latest ITU-T
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823 for PCM 30, and I.431
for ISDN primary rate. It also meets or supports ETSI
ETS 300 011, ETS 300 166 and ETS 300 233 as well
as BS 6450.
Applications
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E1 add/drop multiplexers and channel banks
CO and PBX equipment interfaces
Primary Rate ISDN nodes
Digital Cross-connect Systems (DCS)
TxDL TxDLCLK
TxMF
TAIS
DSTi
CSTi
Tdi
Tdo
Tms
Tclk
Trst
INT/MOT
IRQ
D7~D0
AC4
~AC0
R/W
/
WR
CS
DS/RD
DSTo
CSTo
IEEE
1149.1
ST-BUS
Interface
Transmit Framing, Error and
Test Signal Generation
Pulse
Generator
Line
Driver
TTIP
TRING
National
Bit Buffer
Data Link,
HDLC0,
HDLC1
Jitter Attenuator
& Clock Control
CAS
Buffer
Clock,Data
Recovery
DG Loop
MT
Loop
ST Loop
RM
Loop
PL Loop
Microprocessor
Interface
MS/FR
M/S
OSC1
OSC2
Rx Equalizer
& Data Slicer
RTIP
RRING
ST-BUS
Interface
Receive Framing, Performance Monitoring,
Alarm Detection, 2 Frame Slip Buffer
RxDLCLK RxDL
RxMF
LOS
RxFP/Rx64kCK
E2o F0b C4b
Figure 1 - Functional Block Diagram
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