MT8888CE-1 Datasheet

IC型號(hào)：
MT8888CE-1
PDF描述：
Integrated DTMFTransceiver with Intel Micro Interface
文件大小：
305.74KB
PDF頁數(shù)：
16頁
芯片廠家：
MITEL

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MT8888C/MT8888C-1

Integrated DTMF Transceiver

with Intel Micro Interface

Features

鈥?/div>

Central office quality DTMF transmitter/receiver

Low power consumption

High speed Intel micro interface

Adjustable guard time

Automatic tone burst mode

Call progress tone detection to -30dBm

ISSUE 2

May 1995

Ordering

MT8888CE/CE-1

MT8888CC/CC-1

MT8888CS/CS-1

MT8888CN/CN-1

Information

20 Pin Plastic DIP

20 Pin Ceramic DIP

20 Pin SOIC

24 Pin SSOP

-40擄C to +85擄C

The receiver section is based upon the industry

standard MT8870 DTMF receiver while the

transmitter utilizes a switched capacitor D/A

converter for low distortion, high accuracy DTMF

signalling. Internal counters provide a burst mode

such that tone bursts can be transmitted with precise

timing. A call progress filter can be selected allowing

a microprocessor to analyze call progress tones.

The MT8888C utilizes an Intel micro interface, which

allows the device to be connected to a number of

popular microcontrollers with minimal external logic.

The MT8888C-1 is functionally identical to the

MT8888C except the receiver is enhanced to accept

lower level signals, and also has a specified low

signal rejection level.

Applications

鈥?/div>

Credit card systems

Paging systems

Repeater systems/mobile radio

Interconnect dialers

Personal computers

Description

The MT8888C is a monolithic DTMF transceiver with

call progress filter. It is fabricated in CMOS

technology offering low power consumption and high

reliability.

TONE

鈭?/div>

D/A

Converters

Row and

Column

Counters

Transmit Data

Status

Data

Bus

Buffer

Tone Burst

Gating Cct.

IN+

IN-

OSC1

OSC2

Oscillator

Circuit

Bias

Circuit

Ref

Dial

Tone

Filter

Control

Logic

Interrupt

Logic

IRQ/CP

High Group

Filter

Low Group

Filter

Control

Logic

Digital

Algorithm

and Code

Converter

Control

I/O

Control

R/W

RS0

Steering

Logic

Receive Data

ESt

St/GT

Figure 1 - Functional Block Diagram

4-91

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