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MT8888CP1 Datasheet

  • MT8888CP1

  • Integrated DTMF Transceiver with Intel Micro Interface

  • 537.32KB

  • 25頁

  • ZARLINK   ZARLINK

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MT8888C
Integrated DTMF Transceiver
with Intel Micro Interface
Data Sheet
Features
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Central office quality DTMF transmitter/receiver
Low power consumption
High speed Intel micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30 dBm
Ordering Information
MT8888CE
20 Pin PDIP
MT8888CS
20 Pin SOIC
MT8888CN
24 Pin SSOP
MT8888CP
28 Pin PLCC
MT8888CE1
20 Pin PDIP*
MT8888CS1
20 Pin SOIC*
MT8888CN1
24 Pin SSOP*
MT8888CP1
28 Pin PLCC*
MT8888CPR
28 Pin PLCC
MT8888CSR
20 Pin SOIC
MT8888CSR1 20 Pin SOIC*
MT8888CPR1 28 Pin PLCC*
*Pb Free Matte Tin
-40擄C to +85擄C
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape &
Tape &
Tape &
Tape &
September 2005
Applications
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Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Reel
Reel
Reel
Reel
Description
The MT8888C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8888C utilizes an Intel micro interface, which
allows the device to be connected to a number of
popular microcontrollers with minimal external logic.
TONE
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D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Data
Bus
Buffer
D0
D1
D2
D3
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
IRQ/CP
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
Control
Register
A
Control
Register
B
I/O
Control
RD
CS
WR
RS0
Steering
Logic
Receive Data
Register
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.

MT8888CP1 產(chǎn)品屬性

  • 0現(xiàn)貨

  • 停產(chǎn)

  • -

  • 管件

  • 停產(chǎn)

  • DTMF 收發(fā)器

  • -

  • 1

  • 4.75V ~ 5.25V

  • 7mA

  • -

  • -40°C ~ 85°C

  • 表面貼裝型

  • 28-LCC（J 形引線）

  • 28-PLCC

MT8888CP1相關(guān)型號PDF文件下載

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