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MT5C1009DCJ-20/883C Datasheet

  • MT5C1009DCJ-20/883C

  • 128K x 8 SRAM WITH CHIP & OUTPUT ENABLE

  • 17頁(yè)

  • ETC

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SRAM
Austin Semiconductor, Inc.
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
鈥MD 5962-89598
鈥IL-STD-883
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MT5C1009
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Access Times: 15, 20, 25, 35, 45, 55 and 70 ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
32-Pin LCC (ECA)
4 3 2 1 32 31 30
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
OPTIONS
鈥?Timing
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
鈥?Package(s)鈥?/div>
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
鈥?2V data retention/low power
MARKING
-15
-20
-25
-35
-45
-55*
-70*
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
A12
A14
A10
6
NC
V
CC
A15
CE2
NC
32-Pin Flat Pack (F)
29
28
27
26
25
24
23
22
21
WE
\
A13
A8
A9
A11
OE
\
A10
CE1
\
DQ8
14 15 16 17 18 19 20
DQ2
DQ3
V
SS
DQ4
DQ5
DQ6
DQ7
GENERAL DESCRIPTION
C
CW
EC
ECA
F
DCJ
SOJ
L
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design flexibility in high-speed memory
applications, this device offers chip enable (CE\) and output
enable (OE\) features. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The devices offer a reduced power standby mode when dis-
abled, allowing system designs to achieve low standby power
requirements.
The 鈥淟鈥?version offers a 2V data retention mode, re-
ducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1009
Rev. 5.5 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

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