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MT5C1001F-883C Datasheet

  • MT5C1001F-883C

  • SRAM

  • 13頁

  • ETC

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Austin Semiconductor, Inc.
1M x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
鈥?SMD 5962-92316
鈥?MIL-STD-883
MT5C1001
Limited Availability
PIN ASSIGNMENT
(Top View)
SRAM
28-Pin DIP (C)
(400 MIL)
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A9
A8
A7
A6
A5
A4
NC
A3
A2
A1
A0
D
CE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
FEATURES
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
High Speed: 20, 25, 35, and 45
Battery Backup: 2V data retention
Low power standby
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
Three-state output
32-Pin Flat Pack (F)
OPTIONS
鈥?Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
鈥?Package(s)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
MARKING
-20
-25
-35
-45
-55*
-70*
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
C
EC
F
DCJ
No. 109
No. 207
No. 303
No. 501
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The 鈥淟鈥?version provides an approximate 50 percent
reduction in CMOS standby current (I
SBC2
) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
鈥?Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
鈥?2V data retention/low power
L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1001
Rev. 2.0 2/00
1

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