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MT4LC1M16E5TG-6 Datasheet

  • MT4LC1M16E5TG-6

  • EDO DRAM

  • 384.60KB

  • 24頁

  • MICRON

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16Mb: 1 MEG x16
EDO DRAM
EDO DRAM
MT4C1M16E5 鈥?1 Meg x 16, 5V
MT4LC1M16E5 鈥?1 Meg x 16, 3.3V
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/products/datasheets/sdramds.html
FEATURES
鈥?JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
鈥?High-performance CMOS silicon-gate process
鈥?Single power supply (+3.3V 鹵0.3V or 5V 鹵10%)
鈥?All inputs, outputs and clocks are TTL-compatible
鈥?Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN; optional self refresh (S)
鈥?BYTE WRITE access cycles
鈥?1,024-cycle refresh (10 row, 10 column addresses)
鈥?Extended Data-Out (EDO) PAGE MODE access
鈥?5V-tolerant inputs and I/Os on 3.3V devices
PIN ASSIGNMENT (Top View)
44/50-Pin TSOP
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
42-Pin SOJ
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
SS
OPTIONS
鈥?/div>
Voltages
1
3.3V
5V
鈥?Refresh Addressing
1,024 (1K) rows
鈥?Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
鈥?Timing
50ns access
60ns access
鈥?Refresh Rates
Standard Refresh (16ms period)
Self Refresh (128ms period)
鈥?Operating Temperature Range
Commercial (0
o
C to +70
o
C)
Extended (-20
o
C to +80
o
C)
Part Number Example:
MARKING
LC
C
E5
DJ
TG
-5
-6
None
S
2
None
ET
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
V
CC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
SS
NOTE:
The "#" symbol indicates signal is active LOW.
1 MEG x 16 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC1M16E5DJ-x
MT4LC1M16E5DJ-x S
MT4LC1M16E5TG-x
MT4LC1M16E5TG-x S
MT4C1M16E5DJ-x
MT4C1M16E5TG-x
Vcc REFRESH PACKAGE REFRESH
3.3V
1K
400-SOJ Standard
3.3V
1K
400-SOJ
Self
3.3V
1K
400-TSOP Standard
3.3V
1K
400-TSOP
Self
5V
1K
400-SOJ Standard
5V
1K
400-TSOP Standard
NOTE:
鈥?x鈥?indicates speed grade marking under timing
options.
MT4LC1M16E5TG-6
NOTE:
1. The third field distinguishes the low voltage offering: LC desig-
nates Vcc = 3.3V and C designates Vcc = 5V.
2. Available only on MT4LC1M16E5 (3.3V)
GENERAL DESCRIPTION
The 1 Meg x 16 is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x16
configuration. The 1 Meg x 16 has both BYTE WRITE
and WORD WRITE access cycles via two CAS# pins
(CASL# and CASH#). These function like a single CAS#
found on other DRAMs in that either CASL# or CASH#
will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
the last CAS# to transition back HIGH. Using only one
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
15ns
17ns
8ns
10ns
1 Meg x 16 EDO DRAM
D52_B.p65 鈥?Rev. B; Pub. 3/01
1
漏2001, Micron Technology, Inc
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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