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MT48LC4M4A1TGS Datasheet

  • MT48LC4M4A1TGS

  • SYNCHRONOUS DRAM

  • 1768.67KB

  • 50頁

  • MICRON

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16 MEG: x4, x8
SDRAM
SYNCHRONOUS
DRAM
FEATURES
鈥?PC100-compliant; includes CONCURRENT AUTO
PRECHARGE
鈥?Fully synchronous; all signals registered on positive
edge of system clock
鈥?Internal pipelined operation; column address can be
changed every clock cycle
鈥?Internal banks for hiding row access/precharge
鈥?Programmable burst lengths: 1, 2, 4, 8, or full page
鈥?Auto Precharge and Auto Refresh Modes
鈥?Self Refresh Mode
鈥?64ms, 4,096-cycle refresh
鈥?LVTTL-compatible inputs and outputs
鈥?Single +3.3V 鹵0.3V power supply
鈥?Longer lead TSOP for improved reliability (OCPL*)
鈥?One- and two-clock WRITE recovery (
t
WR) versions
MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks
MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks
For the latest data sheet revisions, please refer to the
Micron Web site:
www.micron.com/datasheets.
PIN ASSIGNMENT (Top View)
44-Pin TSOP
x4
-
NC
x8
V
DD
DQ0
VssQ
DQ1
V
DD
Q
DQ2
VssQ
DQ3
V
DD
Q
NC
NC
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
x8
Vss
DQ7
VssQ
DQ6
V
DD
Q
DQ5
VssQ
DQ4
V
DD
Q
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
x4
-
NC
-
DQ0
-
DQ3
-
NC
-
NC
-
DQ1
-
DQ2
OPTIONS
鈥?Configurations
4 Meg x 4 (2 Meg x 4 x 2 banks)
2 Meg x 8 (1 Meg x 8 x 2 banks)
MARKING
4M4
2M8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
鈥?WRITE Recovery (
t
WR/
t
DPL)
t
WR = 1 CLK
A1
t
WR = 2 CLK (Contact factory for availability.)A2
鈥?Plastic Package - OCPL*
44-pin TSOP (400 mil)
鈥?Timing (Cycle Time)
8ns;
t
AC = 6ns @ CL = 3
10ns;
t
AC = 9ns @ CL = 2
NOTE:
The # symbol indicates signal is active LOW. A dash
(-) indicates x4 pin function is same as x8 pin
function.
TG
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4 MEG x 4
2 MEG x 8
2 Meg x 4 x 2 banks 1 Meg x 8 x 2 banks
4K
4K
2K (A0-A10)
2K (A0-A10)
2 (BA)
1 (BA)
1K (A0-A9)
512 (A0-A8)
-8B
-10
NOTE:
The 16Mb SDRAM base number differentiates the
offerings in two places: MT48LC2M8A1 S. The fourth
field distinguishes the architecture offering: 4M4
designates 4 Meg x 4, and 2M8 designates 2 Meg x 8.
The fifth field distinguishes the WRITE recovery
offering: A1 designates one CLK and A2 designates two
CLKs.
Part Number Example:
KEY TIMING PARAMETERS
SPEED
GRADE
-8B
-10
-8B
-10
CLOCK
ACCESS TIME
SETUP
FREQUENCY CL = 2** CL = 3** TIME
125 MHz
100 MHz
83 MHz
66 MHz
鈥?/div>
鈥?/div>
9ns
9ns
6ns
7.5ns
鈥?/div>
鈥?/div>
2ns
3ns
2ns
3ns
HOLD
TIME
1ns
1ns
1ns
1ns
MT48LC2M8A1TG-10 S
16Mb (x4/x8) SDRAM PART NUMBERS
PART NUMBER
MT48LC4M4A1TG S
MT48LC2M8A1TG S
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 鈥?Rev. 5/98
ARCHITECTURE
4 Meg x 4 (
t
WR = 1 CLK)
2 Meg x 8 (
t
WR = 1 CLK)
* Off-center parting line
**CL = CAS (READ) latency
1
漏1998, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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