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MT46V4M32LG Datasheet

  • MT46V4M32LG

  • DOUBLE DATA RATE DDR SDRAM

  • 66頁

  • MICRON

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ADVANCE
鈥?/div>
128Mb: x32
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
鈥?V
DD
= +2.5V 鹵0.125V, V
DD
Q = +2.5V 鹵0.125V
鈥?Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
鈥?Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
鈥?Reduced and matched output drive options
鈥?Differential clock inputs (CK and CK#)
鈥?Commands entered on each positive CK edge
鈥?DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
鈥?DLL to align DQ and DQS transitions with CK
鈥?Four internal banks for concurrent operation
鈥?Data mask (DM) for masking write data
鈥?Programmable burst lengths: 2, 4, 8, or full page
鈥?32ms, 4,096-cycle auto refresh
鈥?Auto precharge option
鈥?Auto Refresh and Self Refresh Modes
鈥?2.5V I/O (SSTL_2 compatible)
鈥?DQS per byte on the FBGA package
鈥?1.8V V
DD
Q option for FBGA package
鈥?/div>
t
RAS lockout
MT46V4M32 - 1 Meg x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
PIN ASSIGNMENT (TOP VIEW)
100-Pin TQFP
DQ2
V
SS
Q
DQ1
DQ0
V
DD
V
DD
Q
DQS
NC \ RFU
V
SS
Q
DNU
NC
NC
NC
NC
V
DD
Q
V
SS
DQ31
DQ30
V
SS
Q
DQ29
10099 98 97 96 95 94 93 9291 90 89 88 87 86 8584 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
DQ3
V
DD
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
DD
Q
DQ16
DQ17
V
SS
Q
DQ18
DQ19
V
DD
Q
V
DD
V
SS
DQ20
DQ21
V
SS
Q
DQ22
DQ23
V
DD
Q
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
DQ28
V
DD
Q
DQ27
DQ26
V
SS
Q
DQ25
DQ24
V
DD
Q
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
DD
Q
V
SS
V
DD
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
DD
Q
V
REF
DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP
OPTIONS
鈥?Configuration
4 Meg x 32 (1 Meg x 32 x 4 banks)
鈥?IO Voltage
2.5V V
DD
Q
1.8V V
DD
Q
鈥?Plastic Packages
100-pin TQFP (0.65mm lead pitch)
12mm x 12mm FBGA
鈥?Timing - Cycle Time
300 MHz @ CL = 5
250 MHz @ CL = 4
200 MHz @ CL = 3
Part Number Example:
MARKING
4M32
None
V1
LG
FK
-33
1
-4
1
-5
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
KEY TIMING PARAMETERS
SPEED
GRADE
-33
-4
-5
CL = 5
1
CLOCK RATE
CL = 4
1
CL = 3
1
DATA-OUT ACCESS
WINDOW
2
WINDOW
DQS-DQ
SKEW
Note: 1. -4 and -33 speed grades are only available in the FBGA package
MT46V4M32V1FK-33
128Mb (x32) DDR SDRAM PART NUMBER
PART NUMBER
MT46V4M32LG
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 鈥?Rev. B, Pub. 7/02
300 MHz 250 MHz
-
0.685ns
-
250 MHz 200 MHz 0.950ns
-
-
200 MHz 1.400ns
A0
A1
A2
A3
V
DD
A10
A11
NC
NC
NC
NC
NC
NC
NC
A9
V
SS
A4
A5
A6
A7
4 Meg x 32
1 Meg x 32 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
256 (A0-A7)
鹵0.6ns +0.40ns
鹵0.7ns +0.45ns
鹵0.7ns +0.45ns
ARCHITECTURE
4 Meg x 32
1. CL = CAS (Read) Latency
2. Minimum clock rate @ max CL
1
漏2002, Micron Technology, Inc.
鈥?/div>
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.

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