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MT46V32M4TG-8L Datasheet

  • MT46V32M4TG-8L

  • DOUBLE DATA RATE DDR SDRAM

  • 68頁(yè)

  • MICRON

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PRELIMINARY
鈥?/div>
128Mb: x4, x8, x16
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
鈥?V
DD
= +2.5V 鹵0.2V, V
DD
Q = +2.5V 鹵0.2V
鈥?Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two 鈥?one per byte)
鈥?Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
鈥?Differential clock inputs (CK and CK#)
鈥?Commands entered on each positive CK edge
鈥?DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
鈥?DLL to align DQ and DQS transitions with CK
鈥?Four internal banks for concurrent operation
鈥?Data mask (DM) for masking write data (x16 has
two 鈥?one per byte)
鈥?x16 has programmable IOL/IOH option
鈥?Programmable burst lengths: 2, 4, or 8
鈥?Auto precharge option
鈥?Auto Refresh and Self Refresh Modes
鈥?Longer lead TSOP for improved reliability (OCPL)
鈥?2.5V I/O (SSTL_2 compatible)
MT46V32M4 鈥?8 Meg x 4 x 4 banks
MT46V16M8 鈥?4 Meg x 8 x 4 banks
MT46V8M16 鈥?2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/datasheets
PIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
x4
x8
x16
V
DD
V
DD
V
DD
NC
DQ0
DQ0
V
DD
Q V
DD
Q
V
DD
Q
NC
DQ1
NC
DQ0
DQ1
DQ2
V
SS
Q
V
SS
Q
VssQ
NC
DQ3
NC
NC
DQ2
DQ4
V
DD
Q V
DD
Q
V
DD
Q
NC
DQ5
NC
DQ1
DQ3
DQ6
V
SS
Q
V
SS
Q
VssQ
NC
DQ7
NC
NC
NC
NC
V
DD
Q V
DD
Q
V
DD
Q
NC
NC
LDQS
NC
NC
NC
V
DD
V
DD
V
DD
NC
DNU
DNU
NC
NC
LDM
WE#
WE#
WE#
CAS#
CAS#
CAS#
RAS#
RAS#
RAS#
CS#
CS#
CS#
NC
NC
NC
BA0
BA0
BA0
BA1
BA1
BA1
A10/AP A10/AP A10/AP
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A3
V
DD
V
DD
V
DD
x16
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
DNU
V
REF
V
SS
UDM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
x8
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
x4
V
SS
NC
V
SS
Q
NC
DQ3
V
DD
Q
NC
NC
V
SS
Q
NC
DQ2
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
OPTIONS
鈥?Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
鈥?Plastic Package 鈥?OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
鈥?Timing 鈥?Cycle Time
7.5ns @ CL = 2 (DDR266B)
1
7.5ns @ CL = 2.5 (DDR266B)
2
10ns @ CL = 2 (DDR200)
3
鈥?Self Refresh
Standard
Low Power
MARKING
32M4
16M8
8M16
TG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
-75Z
-75
-8
none
L
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
32 Meg x 4
8 Meg x 4 x 4 banks
4K
4K (A0鈥揂11)
4 (BA0, BA1)
2K (A0鈥揂9, A11)
16 Meg x 8
8 Meg x 16
4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K
4K
4K (A0鈥揂11)
4K (A0鈥揂11)
4 (BA0, BA1)
4 (BA0, BA1)
1K (A0鈥揂9)
512(A0鈥揂8)
KEY TIMING PARAMETERS
SPEED
CLOCK RATE
CL = 2**
133 MHz
100 MHz
100 MHz
CL = 2.5**
133 MHz
133 MHz
125 MHz
DATA-OUT
2.5ns
2.5ns
3.4ns
ACCESS
鹵0.75ns
鹵0.75ns
鹵0.8ns
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.6ns
GRADE
-75Z
-75
-8
WINDOW* WINDOW
NOTE:
1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
*Minimum clock rate @ CL = 2 (-75Z and -8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 鈥?Rev. C; Pub. 4/01
鈥?PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON鈥橲
PRODUCTION DATA SHEET SPECIFICATIONS.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2001, Micron Technology, Inc.

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