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MT46V2M32V1 Datasheet

  • MT46V2M32V1

  • DOUBLE DATA RATE DDR SDRAM

  • 65頁

  • MICRON

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64Mb: x32
DDR SDRAM
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
鈥?Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
鈥?Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
鈥?Reduced output drive option
鈥?Differential clock inputs (CK and CK#)
鈥?Commands entered on each positive CK edge
鈥?DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
鈥?DLL to align DQ and DQS transitions with CK
鈥?Four internal banks for concurrent operation
鈥?Data mask (DM) for masking write data
鈥?Programmable burst lengths: 2, 4, 8, or full page
鈥?32ms, 4,096-cycle auto refresh (7.8碌s/cycle)
鈥?Auto precharge option
鈥?Auto Refresh and Self Refresh Modes
鈥?Programmable I/O (SSTL_2 compatible) 鈥?reduced
and impedance matched
MT46V2M32V1- 512K x 32 x 4 banks
MT46V2M32 - 512K x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
PIN ASSIGNMENT (TOP VIEW)
100-Pin TQFP
(Normal Bend Shown)
DQ2
V
SS
Q
DQ1
DQ0
V
DD
V
DD
Q
DQS
NC \ RFU
V
SS
Q
DNU
NC
NC
NC
NC
V
DD
Q
V
SS
DQ31
DQ30
V
SS
Q
DQ29
OPTIONS
鈥?Configuration
2 Meg x 32
(512K x 32 x 4 banks)
鈥?Power Supply
2.5V V
DD
/V
DD
Q
2.65V V
DD
/V
DD
Q
鈥?Plastic Package
100-pin TQFP (0.65mm lead pitch)
鈥?Timing - Cycle Time
200 MHz @ CL = 3
183 MHz @ CL = 3
166 MHz @ CL = 3
150 MHz @ CL = 3
Part Number Example:
MARKING
2M32
V1
none
LG
DQ3
V
DD
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
DD
Q
DQ16
DQ17
V
SS
Q
DQ18
DQ19
V
DD
Q
V
DD
V
SS
DQ20
DQ21
V
SS
Q
DQ22
DQ23
V
DD
Q
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
10099 98 97 96 95 94 93 9291 90 89 88 87 86 8584 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
DQ28
V
DD
Q
DQ27
DQ26
V
SS
Q
DQ25
DQ24
V
DD
Q
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
DD
Q
V
SS
V
DD
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
DD
Q
V
REF
DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP
Configuration
-5
-55
-6
-65
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
MT46V2M32V1LG-5
KEY TIMING PARAMETERS
SPEED
GRADE
CLOCK RATE
CL = 2**
125 MHz
100 MHz
100 MHz
100 MHz
CL = 3**
200 MHz
183 MHz
166 MHz
150 MHz
DATA-OUT
1.5ns
1.8ns
1.9ns
2.1ns
ACCESS
鹵0.75ns
鹵0.75ns
鹵0.75ns
鹵0.75ns
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.5ns
+0.5ns
WINDOW* WINDOW
64Mb (x32) DDR SDRAM PART NUMBER
PART NUMBER
MT46V2M32LG
ARCHITECTURE
2 Meg x 32
-5
-55
-6
-65
*Minimum clock rate @ CL = 3
**CL = CAS (Read) Latency
64Mb: x32 DDR SDRAM
2M32DDR-07.p65 鈥?Rev. 12/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
漏2001, Micron Technology, Inc.
A0
A1
A2
A3
V
DD
A10
NC
NC
NC
NC
NC
NC
NC
NC
A9
V
SS
A4
A5
A6
A7
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)

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