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OBSOLETE

4, 8 MEG x 36

PARITY DRAM SIMMs

DRAM

MODULE

FEATURES

鈥?JEDEC- and industry-standard pinout in a 72-pin,

single in-line memory module (SIMM)

鈥?16MB (4 Meg x 36) and 32MB (8 Meg x 36) parity

versions

鈥?High-performance CMOS silicon-gate process

鈥?Single 5V

鹵10%

power supply

鈥?All inputs, outputs and clocks are TTL-compatible

鈥?Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

鈥?2,048-cycle refresh distributed across 32ms

鈥?FAST PAGE MODE (FPM) access cycle

鈥?Multiple RAS# lines allow x18 or x36 widths

MT12D436

MT24D836

PIN ASSIGNMENT (Front View)

72-Pin SIMM

(DD-5) 4 Meg x 36 (shown)

(DD-6) 8 Meg x 36

(DD-7) 4 Meg x 36 Low Profile

OPTIONS

鈥?Timing

60ns access

MARKING

-6

M

G

DM

DG

PIN SYMBOL

PIN SYMBOL

PIN SYMBOL

PIN

1

Vss

19

A10

37

DQ18

55

2

DQ1

20

DQ5

38

DQ36

56

3

DQ19

21

DQ23

39

Vss

57

4

DQ2

22

DQ6

40

CAS0#

58

5

DQ20

23

DQ24

41

CAS2#

59

6

DQ3

24

DQ7

42

CAS3#

60

7

DQ21

25

DQ25

43

CAS1#

61

8

DQ4

26

DQ8

44

RAS0#

62

9

DQ22

27

DQ26

45 NC/RAS1#* 63

10

Vcc

28

A7

46

NC

64

11

NC

29

NC (A11)

47

WE#

65

12

A0

30

Vcc

48

NC

66

13

A1

31

A8

49

DQ10

67

14

A2

32

A9

50

DQ28

68

15

A3

33 NC/RAS3#* 51

DQ11

69

16

A4

34

RAS2#

52

DQ29

70

17

A5

35

DQ27

53

DQ12

71

18

A6

36

DQ9

54

DQ30

72

*32MB version only

SYMBOL

DQ13

DQ31

DQ14

DQ32

Vcc

DQ33

DQ15

DQ34

DQ16

DQ35

DQ17

NC

PRD1

PRD2

PRD3

PRD4

NC

Vss

鈥?Packages

72 -pin SIMM

72 -pin SIMM (gold)

72-pin SIMM low profile (1.00")

72-pin SIMM (gold) low profile (1.00")

KEY TIMING PARAMETERS

SPEED

-6

t

RC

t

RAC

t

PC

t

AA

t

CAC

t

RP

110ns

60ns

35ns

30ns

15ns

40ns

PART NUMBERS

PART NUMBER

MT12D436G-xx

MT12D436M-xx

MT12D436DG-xx

MT12D436DM-xx

MT24D836G-xx

MT24D836M-xx

xx = speed

CONFIGURATION

4 Meg x 36

4 Meg x 36

4 Meg x 36

4 Meg x 36

8 Meg x 36

8 Meg x 36

PLATING

Gold

Tin/Lead

Gold

Tin/Lead

Gold

Tin/Lead

HEIGHT

1.190"

1.190"

1.000"

1.000"

1.190"

1.190"

NOTE:

Symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

GENERAL DESCRIPTION

The MT12D436 and MT24D836 are randomly accessed

16MB and 32MB solid-state memories organized in a x36

configuration. During READ or WRITE cycles, each bit is

uniquely addressed through the 22 address bits, which are

entered 11 bits (A0 -A10) at a time. RAS# is used to latch the

first 11 bits and CAS# the latter 11 bits. A READ or WRITE

4, 8 Meg x 36 Parity DRAM SIMMs

DM45.pm5 鈥?Rev. 3/97

cycle is selected with the WE# input. A logic HIGH on WE#

dictates READ mode, while a logic LOW on WE# dictates

WRITE mode. During a WRITE cycle, data-in (D) is latched

by the falling edge of CAS#. Since WE# goes LOW prior to

CAS# going LOW, the output pin(s) remain open (High-Z)

until the next CAS# cycle.

1

Micron Technology, Inc., reserves the right to change products or specifications without notice.

鈥?997,

Micron Technology, Inc.

next

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