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MP7628BD Datasheet

  • MP7628BD

  • 5 V CMOS Quad Multiplying 8-Bit Digital-to-Analog Converter

  • 12頁

  • EXAR   EXAR

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MP7628
5 V CMOS
Quad Multiplying 8-Bit
Digital-to-Analog Converter
FEATURES
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Readback Capability for all DACs
On-Chip Latches for All DACs
Linearity Grades to +1/8 LSB
Single Supply Voltage (5 Volt)
DACs Matched to 1%
Four Quadrant Multiplication
Microprocessor TTL/CMOS Compatible
Latch-Up Free
Dual Version: MP7529B
APPLICATIONS
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Microprocessor Controlled Gain and Attenuation
Circuits
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Microprocessor Controlled/Programmable
Power Supplies
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Hardware Redundant Applications Requiring
Data Readback
GENERAL DESCRIPTION
The MP7628 is a quad 8-bit Digital-to-Analog Converter de-
signed using a decoded DAC architecture featuring excellent
DAC-to-DAC matching and guaranteed monotonicity.
Separate on-chip latches are provided for each DAC to allow
easy microprocessor interface.
The readback function allows the user to poll or read the data
latches, eliminating the need for storing information in RAM. In
the event the microprocessor power supply is interrupted, it can
poll the DACs to establish the last known system state.
Data is transferred into any of the four DAC data latches via
common 8-bit TTL/CMOS compatible input port. Control inputs
DS1, DS2 and A/B determine which DAC is to be loaded. The
MP7628鈥檚 load cycle is similar to the write cycle of a random ac-
cess memory and the device is bus compatible with most 8-bit
microprocessors.
The device operates at +5 V power supply and dissipates
less than 5mW.
All DACs offer excellent four quadrant multiplication charac-
teristics with a separate reference input and feedback resistor
for each DAC.
SIMPLIFIED BLOCK DIAGRAM
V
DD
LATCH A
DAC A
V
REFB
V
REFA
R
FB
R
FBA
I
OUT1A
I
OUT2A
/
I
OUT2B
DAC B
DB0
(LSB)
DATA BUS
DB7
(MSB)
THREE-STATE
BUFFER
BI-
DIRECTIONAL
LINE
DRIVER
LATCH B
I
OUT1B
R
FB
R
FB
R
FBB
R
FBC
I
OUT1C
I
OUT2C
/
I
OUT2D
THREE-STATE
BUFFER
LATCH C
DAC C
THREE-STATE
BUFFER
A/B
R/W
DS1
DS2
THREE-STATE
BUFFER
CONTROL
LOGIC
LATCH D
DAC D
I
OUT1D
R
FB
R
FBD
GND
V
REFC
V
REFD
Rev. 2.00
1

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