MEMORY MODULE
SDRam 128Mx16-SOP
Synchronous Dynamic Ram
MODULE
MMSD16128808S-V
2Gbit SDRam organized as 128Mx16, based on 32Mx8
Pin Assignment (Top View)
SOP 58 - (Pitch : 0.80 mm)
Features
- Stack of eight 256Mbit SDRam.
- Organized as 128Mx16-bit.
- Single +3.3V 鹵0.3V power supply.
- Fully synchronous ; all signals registered on positive edge of
system clock.
- Internal pipelined operation ; column adress can be changed
every clock cycle.
- Programmable burst lengths ; 1, 2, 4, 8 or full page.
- Auto Precharge, includes Concurrent Auto Precharge, and
Auto Refresh Modes.
- Self Refresh Modes.
- LVTTL-compatible inputs and outputs.
- Available Temperature Range :
0擄C to +70擄C
-40擄C to +85擄C
- Available with screening option for high reliability application
(Space, etc...).
Bank 0, #CS0
Bank 1, #CS1
Bank 2, #CS2
Bank 3, #CS3
1
CLK0, CKE0
3
5
7
CLK1, CKE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VDD
DQ0
VDDQ
DQ8
DQ1
VSSQ
DQ9
DQ2
VDDQ
DQ10
DQ3
VSSQ
DQ11
VDD
#CS1
#WE
#CAS
#RAS
#CS0
BA0
21
BA1
41
CKE0
22
A10/AP
42
CLK0
23
A0
43
DQM0
A1
24
44
DQM1
25
45
VSS
A2
26
A3
46
DQ15
27
VDD
47
VDDQ
28
#CS2
48
DQ4
29
#CS3
49
DQ14
30
CLK1
50
VSSQ
31
CKE1
51
DQ5
32
VSS
52
DQ13
33
A4
53
VDDQ
A5
54
DQ6
34
35
A6
55
DQ12
A7
56
VSSQ
36
A8
37
57
DQ7
A9
38
58
VSS
A11
39
A12
40
FUNCTIONAL BLOCK DIAGRAM
General description
The MMSD16128808S-V is a high-speed highly integrated
Synchronous Dynamic Random Access Memory containing
2,147,483,648 bits.
It is organized with four banks of 512 Mbit.
Each bank has a 16-bit interface and is selected with specific #CS
CLK and CKE.
It is particularly well suited for use in high reliability, high
performance and high density system applications, such as
solid state mass recorder, server or workstation.
The MMSD16128808S-V is
packaged in a 58 pin SOP.
DQM0
DQ0-DQ7
2
DQM1
DQ8-DQ15
4
6
8
CLK0, CKE0
CLK1, CKE1
(All others signals are common to the eight memories)
SDRam Memory Module
ULYSSE
(3DSD2048-163)
3D PLUS S.A. reserves the right to change or cancel products or specifications without notice
3DFP-0014-REV : 4 - SEPT. 2003
1
2
