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MM74HC76N Datasheet

  • MM74HC76N

  • Dual J-K Flip-Flops with Preset and Clear

  • 138.83KB

  • 6頁

  • NSC

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MM54HC76 MM74HC76 Dual J-K Flip-Flops with Preset and Clear
January 1988
MM54HC76 MM74HC76 Dual J-K Flip-Flops
with Preset and Clear
General Description
These high speed (30 MHz minimum) J-K Flip-Flops utilize
advanced silicon-gate CMOS technology to achieve the low
power consumption and high noise immunity of standard
CMOS integrated circuits along with the ability to drive 10
LS-TTL loads
Each flip-flop has independent J K PRESET CLEAR and
CLOCK inputs and Q and Q outputs These devices are
edge sensitive to the clock input and change state on the
negative going transition of the clock pulse Clear and pre-
set are independent of the clock and accomplished by a low
logic level on the corresponding input
The 54HC 74HC logic family is functionally as well as pin-
out compatible with the standard 54LS 74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Typical propagation delay 16 ns
Wide operating voltage range
Low input current 1
mA
maximum
Low quiescent current 40
mA
maximum (74HC Series)
High output drive 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Truth Table
Inputs
PR
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
J
X
X
X
L
H
L
H
X
L
X
X
X
L
L
H
H
X
Outputs
Q
Q
v
v
v
v
H
H
L
L
H
L
L
Q0
Q0
H
L
L
H
TOGGLE
Q0
Q0
This is an unstable condition and is not guaranteed
TL F 5074 鈥?1
Top View
Order Number MM54HC76 or MM74HC76
TL F 5074 鈥?3
TL F 5074 鈥?2
(1 of 2)
C
1995 National Semiconductor Corporation
TL F 5074
RRD-B30M105 Printed in U S A

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