MM54HC74A MM74HC74A Dual D Flip-Flop with Preset and Clear
January 1988
MM54HC74A MM74HC74A
Dual D Flip-Flop with Preset and Clear
General Description
The MM54HC74A MM74HC74A utilizes advanced silicon-
gate CMOS technology to achieve operating speeds similar
to the equivalent LS-TTL part It possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits along with the ability to drive 10 LS-TTL
loads
This flip-flop has independent data preset clear and clock
inputs and Q and Q outputs The logic level present at the
data input is transferred to the output during the positive-go-
ing transition of the clock pulse Preset and clear are inde-
pendent of the clock and accomplished by a low level at the
appropriate input
The 54HC 74HC logic family is functionally and pinout com-
patible with the standard 54LS 74LS logic family All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Typical propagation delay 20 ns
Wide power supply range 2 鈥?6V
Low quiescent current 40
mA
maximum (74HC Series)
Low input current 1
mA
maximum
Fanout of 10 LS-TTL loads
Connection and Logic Diagrams
Dual-In-Line Package
Truth Table
Inputs
PR
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
D
X
X
X
H
L
X
Outputs
Q
H
L
H
H
L
Q0
Q
L
H
H
L
H
Q0
u
u
L
Note
Q0
e
the level of Q before the indicated input condi-
tions were established
This configuration is nonstable that is it will not persist
when preset and clear inputs return to their inactive (high)
level
TL F 5106 鈥?1
Order Number MM54HC74A or MM74HC74A
TL F 5106 鈥?2
C
1995 National Semiconductor Corporation
TL F 5106
RRD-B30M105 Printed in U S A
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