MM54HC195 MM74HC195 4-Bit Parallel Shift Register
November 1995
MM54HC195 MM74HC195
4-Bit Parallel Shift Register
General Description
The MM54HC195 MM74HC195 is a high speed 4-bit SHIFT
REGISTER utilizes advanced silicon-gate CMOS technolo-
gy to achieve the low power consumption and high noise
immunity of standard CMOS integrated circuits along with
the ability to drive 10 LS-TTL loads at LS type speeds
This shift register features parallel inputs parallel outputs J-
K serial inputs SHIFT LOAD control input and a direct
overriding CLEAR This shift register can operate in two
modes PARALLEL LOAD SHIFT from Q
A
towards Q
D
Parallel loading is accomplished by applying the four bits of
data and taking the SHIFT LOAD control input low The
data is loaded into the associated flip flops and appears at
the outputs after the positive transition of the clock input
During parallel loading serial data flow is inhibited Serial
shifting occurs synchronously when the SHIFT LOAD con-
trol input is high Serial data for this mode is entered at the
J-K inputs These inputs allow the first stage to perform as a
J-K or TOGGLE flip flop as shown in the truth table
The 54HC 74HC logic family is functionally as well as pin-
out compatible with the standard 54LS 74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Y
Typical operating frequency 45 MHz
Typical propagation delay 16 ns (clock to Q)
Wide operating supply voltage range 2 鈥?6V
Low input current 1
mA
maximum
Low quiescent current 80
mA
maximum (74HC Series)
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL F 5324 鈥?1
Top View
Order Number MM54HC195 or MM74HC195
Function Table
Inputs
Clear Shift Clock
Load
L
H
H
H
H
H
H
X
L
H
H
H
H
H
X
Serial
J
X
X
X
L
L
H
H
K
X
X
X
H
L
H
L
Parallel
A B C D
X
a
X
X
X
X
X
X
b
X
X
X
X
X
X
c
X
X
X
X
X
Q
A
Outputs
Q
B
Q
C
Q
D
Q
D
H
d
Q
D0
Q
Cn
Q
Cn
Q
Cn
Q
Cn
H
e
high level (steady state)
L
e
low level (steady state)
X
e
irrelevant (any input including transitions)
e
transition from low to high level
a b c d
e
the level of steady-state input at inputs A B C
or D respectively
Q
A0
Q
B0
Q
C0
Q
D0
e
the level of Q
A
Q
B
Q
C
or Q
D
respectively before the indicated steady-state input condi-
tions were established
Q
An
Q
Bn
Q
Cn
e
the level of Q
A
Q
B
Q
C
respectively
before the most-recent transition of the clock
u
u
L
u
u
u
u
X L
L
L
L
d a
b
c
d
X Q
A0
Q
B0
Q
C0
Q
D0
X Q
A0
Q
A0
Q
Bn
Q
Cn
X L Q
An
Q
Bn
Q
Cn
X H Q
An
Q
Bn
Q
Cn
X Q
An
Q
An
Q
Bn
Q
Cn
C
1995 National Semiconductor Corporation
TL F 5324
RRD-B30M115 Printed in U S A
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