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MM74HC154 Datasheet

  • MM74HC154

  • 4-to-16 Line Decoder

  • 6頁(yè)

  • NSC

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MM54HC154 MM74HC154 4-to-16 Line Decoder
September 1990
MM54HC154 MM74HC154
4-to-16 Line Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technol-
ogy and is well suited to memory address decoding or data
routing applications It possesses high noise immunity and
low power consumption of CMOS with speeds similar to low
power Schottky TTL circuits
The MM54HC154 MM74HC154 have 4 binary select inputs
(A B C and D) If the device is enabled these inputs deter-
mine which one of the 16 normally high outputs will go low
Two active low enables (G1 and G2) are provided to ease
cascading of decoders with little or no external logic
Each output can drive 10 low power Schottky TTL equiva-
lent loads and is functionally and pin equivalent to the
54LS154 74LS154 All inputs are protected from damage
due to static discharge by diodes to V
CC
and ground
Features
Y
Y
Y
Y
Typical propagation delay 21 ns
Power supply quiescent current 80
mA
(74HC)
Wide power supply voltage range 2 鈥?6V
Low input current 1
mA
maximum
Connection Diagram
Dual-In-Line Package
TL F 5122 鈥?1
Top View
Order Number MM54HC154 or MM74HC154
Truth Table
Inputs
G1
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
All others high
G2
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
D
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
Low
Output
C
1995 National Semiconductor Corporation
TL F 5122
RRD-B30M105 Printed in U S A

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