MM54HC147 MM74HC147 10-to-4 Line Priority Encoder
November 1995
MM54HC147 MM74HC147
10-to-4 Line Priority Encoder
General Description
This high speed 10-to-4 Line Priority Encoder utilizes ad-
vanced silicon-gate CMOS technology It possesses the
high noise immunity and low power consumption of stan-
dard CMOS integrated circuits This device is fully buffered
giving it a fanout of 10 LS-TTL loads
The MM54HC147 MM74HC147 features priority encoding
of the inputs to ensure that only the highest order data line
is encoded Nine input lines are encoded to a four line BCD
output The implied decimal zero condition requires no input
condition as zero is encoded when all nine data lines are at
a high logic level All data inputs and outputs are active at
the low logic level
The 54HC 74HC logic family is functionally as well as pin-
out compatible with the standard 54LS 74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Low quiescent power consumption 40
mW
maximum at
25 C
High speed 31 ns propagation delay (typical)
Low input current 1
mA
maximum
Wide supply range 2V to 6V
Connection and Logic Diagrams
Dual-In-Line Package
TL F 5007 鈥?
Top View
Order Number MM54HC147 or MM74HC147
Truth Table
Inputs
1
H
X
X
X
X
X
X
X
X
L
2
H
X
X
X
X
X
X
X
L
H
3
H
X
X
X
X
X
X
L
H
H
4
H
X
X
X
X
X
L
H
H
H
5
H
X
X
X
X
L
H
H
H
H
6
H
X
X
X
L
H
H
H
H
H
7
H
X
X
L
H
H
H
H
H
H
8
H
X
L
H
H
H
H
H
H
H
9
H
L
H
H
H
H
H
H
H
H
D
H
L
L
H
H
H
H
H
H
H
Outputs
C
H
H
H
L
L
L
L
H
H
H
B
H
H
H
L
L
H
H
L
L
H
A
H
L
H
L
H
L
H
L
H
L
TL F 5007 鈥?2
H
e
High Logic Level L
e
Low Logic Level X
e
Irrelevant
C
1995 National Semiconductor Corporation
TL F 5007
RRD-B30M115 Printed in U S A
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