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MM74HC137N Datasheet

  • MM74HC137N

  • 3-to-8 Line Decoder With Address Latches (Inverted Output)

  • 125.50KB

  • 6頁

  • NSC

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MM54HC137 MM74HC137 3-to-8 Line
Decoder With Address Latches (Inverted Output)
November 1995
MM54HC137 MM74HC137 3-to-8 Line
Decoder With Address Latches
(Inverted Output)
General Description
This device utilizes advanced silicon-gate CMOS technolo-
gy to implement a three-to-eight line decoder with latches
on the three address inputs When GL goes from low to
high the address present at the select inputs (A B and C) is
stored in the latches As long as GL remains high no ad-
dress changes will be recognized Output enable controls
G1 and G2 control the state of the outputs independently of
the select or latch-enable inputs All of the outputs are high
unless G1 is high and G2 is low The HC137 is ideally suited
for the implementation of glitch-free decoders in stored-ad-
dress applications in bus oriented systems
The 54HC 74HC logic family is speed function and pin-out
compatible with the standard 54LS 74LS logic family All
inputs are protected from damage due to static discharge by
diodes to V
CC
and ground
Features
Y
Y
Y
Y
Typical propagation delay 20 ns
Wide supply range 2 鈥?6V
Latched inputs for easy interfacing
Fanout of 10 LS-TTL loads
Connection and Functional Block Diagrams
Dual-In-Line Package
TL F 5310鈥?
Order Number MM54HC137
or MM74HC137
TL F 5310 鈥?2
C
1995 National Semiconductor Corporation
TL F 5310
RRD-B30M115 Printed in U S A

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