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MM74HC107J Datasheet

  • MM74HC107J

  • MM54HC107/MM74HC107 Dual J-K Flip-Flops with Clear

  • 6頁(yè)

  • NSC

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MM54HC107 MM74HC107 Dual J-K Flip-Flops with Clear
January 1988
MM54HC107 MM74HC107
Dual J-K Flip-Flops with Clear
General Description
These J-K Flip-Flops utilize advanced silicon-gate CMOS
technology to achieve the high noise immunity and low pow-
er dissipation of standard CMOS integrated circuits These
devices can drive 10 LS-TTL loads
These flip-flops are edge sensitive to the clock input and
change state on the negative going transition of the clock
pulse Each one has independent J K CLOCK and CLEAR
inputs and Q and Q outputs CLEAR is independent of the
clock and accomplished by a low level on the input
The 54HC 74HC logic family is functionally as well as pin-
out compatible with the standard 54LS 74LS logic family
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground
Features
Y
Y
Y
Y
Y
Typical propagation delay 16 ns
Wide operating voltage range 2 鈥?6V
Low input current 1
mA
maximum
Low quiescent current 40
mA
(74HC series)
High output drive 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
Truth Table
Inputs
CLR
L
H
H
H
H
H
CLK
X
J
X
L
H
L
H
X
K
X
L
L
H
H
X
Outputs
Q
Q
v
v
v
v
H
L
H
Q0
Q0
H
L
L
H
TOGGLE
Q0
Q0
TL F 5304 鈥?1
Order Number MM54HC107 or MM74HC107
Logic Diagram
TL F 5304 鈥?3
TL F 5304 鈥?2
C
1995 National Semiconductor Corporation
TL F 5304
RRD-B30M105 Printed in U S A

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