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MM74HC02SJ Datasheet

  • MM74HC02SJ

  • Quad 2-Input NOR Gate

  • 6頁

  • FAIRCHILD

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MM74HC02 Quad 2-Input NOR Gate
September 1983
Revised February 1999
MM74HC02
Quad 2-Input NOR Gate
General Description
The MM74HC02 NOR gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits. All gates have buffered outputs,
providing high noise immunity and the ability to drive 10
LS-TTL loads. The 74HC logic family is functionally as well
as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
s
Typical propagation delay: 8 ns
s
Wide power supply range: 2鈥?V
s
Low quiescent supply current: 20
碌A
maximum
(74HC Series)
s
Low input current: 1
碌A
maximum
s
High output current: 4 mA minimum
Ordering Code:
Order Number
MM74HC02M
MM74HC02SJ
MM74HC02MTC
MM74HC02N
Package Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150鈥?Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code. (Tape and Reel not available in N14A.)
Connection Diagram
Pin Assignment for DIP, SOIC, SOP and TSSOP
Top View
Logic Diagram
漏 1999 Fairchild Semiconductor Corporation
DS005294.prf
www.fairchildsemi.com

MM74HC02SJ 產(chǎn)品屬性

  • 47

  • 集成電路 (IC)

  • 邏輯 - 柵極和逆變器

  • 74HC

  • 或非門

  • 4

  • 2

  • -

  • 2 V ~ 6 V

  • 2µA

  • 5.2mA，5.2mA

  • 0.5 V ~ 1.8 V

  • 1.5 V ~ 4.2 V

  • 15ns @ 6V，50pF

  • -40°C ~ 85°C

  • 表面貼裝

  • 14-SOIC

  • 14-SOIC（0.209"，5.30mm 寬）

  • 管件

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