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MM74C86N Datasheet

  • MM74C86N

  • Quad 2-Input EXCLUSIVE-OR Gate

  • 4頁

  • NSC

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MM54C86 MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
February 1988
MM54C86 MM74C86 Quad 2-Input EXCLUSIVE-OR Gate
General Description
Employing complementary MOS (CMOS) transistors to
achieve wide power supply operating range low power con-
sumption and high noise margin these gates provide basic
functions used in the implementation of digital integrated
circuit systems The N- and P-channel enhancement mode
transistors provide a symmetrical circuit with output swing
essentially equal to the supply voltage No DC power other
than that caused by leakage current is consumed during
static condition All inputs are protected from damage due
to static discharge by diode clamps to V
CC
and GND
Features
Y
Y
Y
Y
Y
Y
Wide supply voltage range
3 0V to 15V
Guaranteed noise margin
1 0V
High noise immunity
0 45 V
CC
(typ )
Low power
Fan out of 2
TTL compatibility
driving 74L
Low power consumption
10 nW package (typ )
The MM54C86 MM74C86 follows the
MM54LS86 MM74LS86 Pinout
Connection Diagram
Dual-In-Line Package
TL F 5887 鈥?
Top View
Order Number MM54C86 or MM74C86
Truth Table
Inputs
A
L
L
H
H
H
e
High Level
Output
B
L
H
L
H
L
e
Low Level
Y
L
H
H
L
C
1995 National Semiconductor Corporation
TL F 5887
RRD-B30M105 Printed in U S A

MM74C86N 產(chǎn)品屬性

  • Fairchild Semiconductor

  • XOR

  • 74C

  • 4

  • 2 / 1

  • - 8 mA

  • 8 mA

  • 185 ns, 90 ns

  • 15 V

  • 3 V

  • + 125 C

  • Through Hole

  • PDIP-14

  • Rail

  • - 55 C

  • 2

  • 1

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