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MM74C74N Datasheet

  • MM74C74N

  • Dual D-Type Flip-Flop

  • 72.04KB

  • 7頁

  • FAIRCHILD

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MM74C74 Dual D-Type Flip-Flop
October 1987
Revised January 1999
MM74C74
Dual D-Type Flip-Flop
General Description
The MM74C74 dual D-type flip-flop is a monolithic comple-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement transistors. Each flip-flop
has independent data, preset, clear and clock inputs and Q
and Q outputs. The logic level present at the data input is
transferred to the output during the positive going transition
of the clock pulse. Preset or clear is independent of the
clock and accomplished by a low level at the preset or clear
input.
s
High noise immunity:
0.45 V
CC
(typ.)
s
Low power: 50 nW (typ.)
s
Medium speed operation: 10 MHz (typ.) with 10V
supply
Applications
鈥?Automotive
鈥?Data terminals
鈥?Instrumentation
鈥?Medical electronics
鈥?Alarm system
Features
s
Supply voltage range:
3V to 15V
2
鈥?Industrial electronics
鈥?Remote metering
鈥?Computers
s
Tenth power TTL compatible: Drive 2 LPT L loads
Ordering Code:
Order Number
MM74C74M
MM74C74N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150鈥?Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
Preset
0
0
1
1
Clear
0
1
0
1
Q
n
0
1
0
Q
n
(Note 1)
Q
n
0
0
1
Q
n
(Note 1)
Note 1:
No change in output from previous state.
Note: A logic 鈥?鈥?on clear sets Q to logic 鈥?鈥?
A logic 鈥?鈥?on preset sets Q to logic 鈥?鈥?
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005885.prf
www.fairchildsemi.com

MM74C74N 產(chǎn)品屬性

  • 25

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74C

  • 設置（預設）和復位

  • D 型

  • 差分

  • 2

  • 1

  • 8MHz

  • 70ns

  • 正邊沿

  • 8mA，8mA

  • 3 V ~ 15 V

  • -55°C ~ 125°C

  • 通孔

  • 14-DIP（0.300"，7.62mm）

  • 管件

  • 74C7474C74N

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