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MM74C373N Datasheet

  • MM74C373N

  • 3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop

  • 11頁(yè)

  • FAIRCHILD

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MM74C373 鈥?MM74C374 3-STATE Octal D-Type Latch 鈥?3-STATE Octal D-Type Flip-Flop
October 1987
Revised January 1999
MM74C373 鈥?MM74C374
3-STATE Octal D-Type Latch 鈥?/div>
3-STATE Octal D-Type Flip-Flop
General Description
The MM74C373 and MM74C374 are integrated, comple-
mentary MOS (CMOS), 8-bit storage elements with 3-
STATE outputs. These outputs have been specially
designed to drive high capacitive loads, such as one might
find when driving a bus, and to have a fan out of 1 when
driving standard TTL. When a high logic level is applied to
the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signals are present at
the other inputs and the state of the storage elements.
The MM74C373 is an 8-bit latch. When LATCH ENABLE is
high, the Q outputs will follow the D inputs. When LATCH
ENABLE goes low, data at the D inputs, which meets the
set-up and hold time requirements, will be retained at the
outputs until LATCH ENABLE returns high again.
The MM74C374 is an 8-bit, D-type, positive-edge triggered
flip-flop. Data at the D inputs, meeting the set-up and hold
time requirements, is transferred to the Q outputs on posi-
tive-going transitions of the CLOCK input.
Both the MM74C373 and the MM74C374 are being assem-
bled in 20-pin dual-in-line packages with 0.300鈥?pin cen-
ters.
Features
s
Wide supply voltage range:
s
High noise immunity:
s
TTL compatibility:
Fan out of 1driving standard TTL
s
Bus driving capability
s
3-STATE outputs
s
Eight storage elements in one package
s
Single CLOCK/LATCH ENABLE and OUTPUT DIS-
ABLE control inputs
s
20-pin dual-in-line package with 0.300鈥?centers takes
half the board space of a 24-pin package
s
Low power consumption
3V to 15V
0.45 V
CC
(typ.)
Ordering Code:
Order Number
MM74C373M
MM74C373N
MM74C374M
MM74C374N
Package Number
M20B
N20A
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300鈥?Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300鈥?Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 1999 Fairchild Semiconductor Corporation
DS005906.prf
www.fairchildsemi.com

MM74C373N 產(chǎn)品屬性

  • 18

  • 集成電路 (IC)

  • 邏輯 - 鎖銷

  • 74C

  • D 型透明鎖存器

  • 8:8

  • 三態(tài)

  • 3 V ~ 15 V

  • 1

  • 70ns

  • 24mA，24mA

  • -55°C ~ 125°C

  • 通孔

  • 20-DIP（0.300"，7.62mm）

  • 20-DIP

  • 管件

  • 74C37374C373N

MM74C373N相關(guān)型號(hào)PDF文件下載

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  • 英文版
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    Quad 2-Input NAND Gate . Quad 2-Input NOR Gate . Hex Inverte...
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    Quad 2-Input NAND Gate, Quad 2-Input NOR Gate, Hex Inverter,...
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    NSC
  • 英文版
    Quad 2-Input NAND Gate, Quad 2-Input NOR Gate, Hex Inverter,...
    NSC [Natio...
  • 英文版
    Quad 2-Input NAND Gate . Quad 2-Input NOR Gate . Hex Inverte...
    FAIRCHILD ...
  • 英文版
    Quad 2-Input NAND Gate . Quad 2-Input NOR Gate . Hex Inverte...
    FAIRCHILD
  • 英文版
    Quad 2-Input NAND Gate, Quad 2-Input NOR Gate, Hex Inverter,...
    NSC
  • 英文版
    Quad 2-Input NAND Gate, Quad 2-Input NOR Gate, Hex Inverter,...
    NSC [Natio...
  • 英文版
    Quad 2-Input NAND Gate . Quad 2-Input NOR Gate . Hex Inverte...
    FAIRCHILD ...
  • 英文版
    Quad 2-Input AND Gate
    FAIRCHILD
  • 英文版
    Quad 2-Input AND Gate
    NSC
  • 英文版
    Quad 2-Input AND Gate
    NSC [Natio...
  • 英文版
    Quad 2-Input AND Gate
    FAIRCHILD ...
  • 英文版
    Quad 2-Input NAND Gate, Quad 2-Input NOR Gate, Hex Inverter,...
    NSC
  • 英文版
    Quad 2-Input NAND Gate, Quad 2-Input NOR Gate, Hex Inverter,...
    NSC [Natio...
  • 英文版
    Hex Schmitt Trigger
    NSC

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