MM74C32 Quad 2-Input OR Gate
October 1987
Revised January 1999
MM74C32
Quad 2-Input OR Gate
General Description
The MM74C32 employs complementary MOS (CMOS)
transistors to achieve low power and high noise margin,
these gates provide the basic functions used in the imple-
mentation of digital integrated circuit systems. The N- and
P-channel enhancement mode transistors provide a sym-
metrical circuit with output swings essentially equal to the
supply voltage. This results in high noise immunity over a
wide supply voltage range. No DC power other than that
caused by leakage current is consumed during static con-
ditions. All inputs are protected against static discharge
damage.
Features
s
Wide supply voltage range:
s
Guaranteed noise margin:
s
High noise immunity:
3.0V to 15V
1.0V
fan out of 2 driving 74L
0.45V V
CC
(typ.)
s
Low power TTL compatibility:
Ordering Code:
Order Number
MM74C32M
MM74C32N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150鈥?Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300鈥?Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Top View
漏 1999 Fairchild Semiconductor Corporation
DS005881.prf
www.fairchildsemi.com
1
2
3
4
