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MM54C165 Datasheet

  • MM54C165

  • Parallel-Load 8-Bit Shift Register

  • 6頁

  • NSC

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MM54C165 MM74C165 Parallel-Load 8-Bit Shift Register
December 1992
MM54C165 MM74C165
Parallel-Load 8-Bit Shift Register
General Description
The MM54C165 MM74C165 functions as an 8-bit parallel-
load serial shift register Data is loaded into the register
independent of the state of the clock(s) when PARALLEL
LOAD (PL) is low Shifting is inhibited as long as PL is low
Data is sequentially shifted from complementary outputs Q
7
and Q
7
highest-order bit (P7) first New serial data may be
entered via the SERIAL DATA (Ds) input Serial shifting oc-
curs on the rising edge of CLOCK1 or CLOCK2 Clock in-
puts may be used separately or together for combined
clocking from independent sources Either clock input may
be used also as an active-low clock enable To prevent dou-
ble-clocking when a clock input is used as an enable the
enable must be changed to a high level (disabled) only while
the clock is high
Features
Y
Y
Y
Y
Wide supply voltage range
Guaranteed noise margin
High noise immunity
Low power TTL compatibility
Parallel loading independent of clock
Dual clock inputs
Fully static operation
3V to 15V
1V
0 45 V
CC
(typ )
fan out of 2
driving 74L
Y
Y
Y
Connection and Block Diagrams
Dual-In-Line Package
TL F 5897 鈥?2
Order Number MM54C165 or MM74C165
Please look into Section 8 Appendix D
for availability of various package types
TL F 5897 鈥?1
Top View
TL F 5897 鈥?3
C
1995 National Semiconductor Corporation
TL F 5897
RRD-B30M105 Printed in U S A

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