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MAX500ACPE+ Datasheet

  • MAX500ACPE+

  • IC, 8BIT DAC, DIP16, 500; Resolution (Bits):8bit; Input Chan...

  • 127.60KB

  • 12頁

  • Maxim   Maxim

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19-1016; Rev 2; 2/96
CMOS, Quad, Serial-Interface
8-Bit DAC
_______________General Description
The MAX500 is a quad, 8-bit, voltage-output digital-to-
analog converter (DAC) with a cascadable serial inter-
face. The IC includes four output buffer amplifiers and
input logic for an easy-to-use, two- or three-wire serial
interface. In a system with several MAX500s, only one
serial data line is required to load all the DACs by cas-
cading them. The MAX500 contains double-buffered
logic and a 10-bit shift register that allows all four DACs
to be updated simultaneously using one control signal.
There are three reference inputs so the range of two of
the DACs can be independently set while the other two
DACs track each other.
The MAX500 achieves 8-bit performance over the full
operating temperature range without external trimming.
____________________________Features
o
Buffered Voltage Outputs
o
Double-Buffered Digital Inputs
o
Microprocessor and TTL/CMOS Compatible
o
Requires No External Adjustments
o
Two- or Three-Wire Cascadable Serial Interface
o
16-Pin DIP/SO Package and 20-Pin LCC
o
Operates from Single or Dual Supplies
MAX500
______________Ordering Information
TEMP. RANGE PIN-PACKAGE ERROR (LSB)
PART
MAX500ACPE
0擄C to +70擄C
16 Plastic DIP
鹵1
MAX500BCPE
MAX500ACWE
MAX500BCWE
MAX500BC/D
MAX500AEPE
MAX500BEPE
MAX500AEWE
MAX500BEWE
MAX500AEJE
MAX500BEJE
MAX500AMJE
MAX500BMJE
MAX500AMLP
MAX500BMLP
0擄C to +70擄C
0擄C to +70擄C
0擄C to +70擄C
0擄C to +70擄C
-40擄C to +85擄C
-40擄C to +85擄C
-40擄C to +85擄C
-40擄C to +85擄C
-40擄C to +85擄C
-40擄C to +85擄C
-55擄C to +125擄C
-55擄C to +125擄C
-55擄C to +125擄C
-55擄C to +125擄C
16 Plastic DIP
16 Wide SO
16 Wide SO
Dice*
16 Plastic DIP
16 Plastic DIP
16 Wide SO
16 Wide SO
16 CERDIP
16 CERDIP
16 CERDIP
16 CERDIP
20 LCC
20 LCC
鹵2
鹵1
鹵2
鹵2
鹵1
鹵2
鹵1
鹵2
鹵1
鹵2
鹵1
鹵2
鹵1
鹵2
________________________Applications
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
________________Functional Diagram
SRO
V
REF
C
AGND
DGND V
SS
V
DD
LDAC V
REF
A/B V
REF
D
V
OUT
A
INPUT
REG A
DAC
REG A
DAC A
*Contact factory for dice specifications.
_________________Pin Configurations
V
OUT
B
TOP VIEW
V
OUT
B
1
16
V
OUT
C
15
V
OUT
D
14
V
DD
DATA BUS
10/11-
BIT
SHIFT
REGISTER
INPUT
REG B
DAC
REG B
DAC B
V
OUT
C
INPUT
REG C
DAC
REG C
DAC C
V
OUT
A
2
V
SS
3
V
REF
A/B
4
MAX500
13
V
REF
C
12
V
REF
D
11
SRO
10
SCL
9
LOAD
V
OUT
D
INPUT
REG D
CONTROL
LOGIC
DAC
REG D
DAC D
AGND
5
DGND
6
LDAC
7
MAX500
SDA
8
LOAD SDA
SCL
DIP/SO
Pin Configurations continued on last page.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX500ACPE+ 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 25

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器

  • -

  • 2.5µs

  • 8

  • 串行

  • 4

  • 雙 ±

  • -

  • 0°C ~ 70°C

  • 通孔

  • 16-DIP（0.300"，7.62mm）

  • 16-PDIP

  • 管件

  • 4 電壓，單極；4 電壓，雙極

  • *

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