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M74HCT573 Datasheet

  • M74HCT573

  • OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTING)

  • STMicroelectronics   STMicroelectronics

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M74HCT573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 21ns (TYP.) at V
CC
= 4.5V
LOW POWER DISSIPATION:
I
CC
= 4碌A(chǔ)(MAX.) at T
A
=25擄C
COMPATIBLE WITH TTL OUTPUTS :
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
M74HCT573B1R
M74HCT573M1R
T&R
M74HCT573RM13TR
M74HCT573TTR
DESCRIPTION
The M74HCT573 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C
2
MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while OE is at high level the outputs will
be in a high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
The M74HCT573 is designed to directly interface
HSC
2
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/11

M74HCT573 PDF文件相關(guān)型號

M74HCT573B1R,M74HCT573RM13TR,M74HCT573TTR

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