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M74HC245 Datasheet

  • M74HC245

  • OCTAL BUS TRANSCEIVER (3-STATE NON INVERTING)

  • STMicroelectronics   STMicroelectronics

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M54/74HC245/640/643
M54/74HC245/640/643
OCTAL BUS TRANSCEIVER (3-STATE): HC245 NON INVERTING
HC640 INVERTING, HC643 INVERTING/NON INVERTING
.
.
.
.
.
.
.
.
HIGH SPEED
t
PD
= 10 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION
o
I
CC
= 4
碌A(chǔ)
(MAX.) at T
A
= 25 C
HIGH NOISE IMMUNITY
V
NIH
= V
INL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA (MIN)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS245/640/643
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R
M74HCXXXM1R
M74HCXXXB1R
M74HCXXXC1R
DESCRIPTION
The M54/74HC245, HC640 and HC643 utilise
silicon gate C2MOS technology to achive operating
speeds equivalent to LSTTL devices.
Along with the low power dissipation and high noise
2
immunity of standards C MOS integrated circuit, it
possesses the capability to drive 15 LSTTL loads.
These IC鈥檚 are intended for two-way asynchronous
communication between data buses, and the
direction of data trasmission is determined by DIR
input. The enable input (G) can be used to disable
the device so that the buses are effectively isolated.
PIN CONNECTION
(top view)
HC245
HC640
HC643
All input are equipped with protection circuits
against static discharge and transient discharge and
transient excess voltage.
IT IS PROHIBITED TO APPLY A SIGNAL TO A
BUS TERMINAL WHEN IT IS IN OUTPUT MODE
AND WHEN A BUS THERMINAL IS FLOATING
(HIGH IMPEDANCE STATE), IT IS REQUESTED
TO FIX THE INPUT LEVEL BY MEANS OF
EXTERNAL PULL DOWN OR PULL UP
RESISTOR.
October 1993
1/11

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