鈻?/div>
100,000 program/erase cycles per block
Block locking
鈥?All Blocks locked at power-up
鈥?Any combination of Blocks can be locked
with zero latency
鈥?WP
F
for Block Lock-Down
鈥?Absolute Write Protection with V
PPF
= V
SS
Common Flash Interface (CFI)
128Mbit synchronous dynamic RAM
鈥?Organized as 4 Banks of 2 MWords, each
16 bits wide
Synchronous burst read and write
鈥?Fixed Burst Lengths: 1, 2, 4, 8 words or Full
Page
鈥?Burst Types: Sequential and Interleaved.
鈥?Maximum Clock Frequency: 104MHz
鈥?CAS Latency 2, 3
Automatic precharge
Low power features:
鈥?PASR (Partial Array Self Refresh),
鈥?Automatic TCSR (Temperature
Compensated Self Refresh)
鈥?Driver Strength (DS)
鈥?Deep Power-Down Mode
Auto Refresh and Self Refresh
鈻?/div>
Flash memory
鈻?/div>
鈻?/div>
LPSDRAM
鈻?/div>
鈥?Asynchronous Page Read mode
鈥?Random Access: 93ns
鈻?/div>
Programming time
鈥?4碌s typical Word program time using Buffer
Enhanced Factory Program command
Memory organization
鈥?Multiple Bank Memory Array: 64 Mbit
Banks
鈥?Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
鈥?program/erase in one Bank while read in
others
鈥?No delay between read and write
operations
Security
鈥?64-bit unique device number
鈥?2112-bit user programmable OTP Cells
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev. 1
1/26
www.st.com
1
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