M36W108AT
M36W108AB
8 Mbit (1Mb x8, Boot Block) Flash Memory and
1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product
PRELIMINARY DATA
s
SUPPLY VOLTAGE
鈥?V
CCF
= V
CCS
= 2.7V to 3.6V: for Program,
Erase and Read
s
s
ACCESS TIME: 100ns
LOW POWER CONSUMPTION
鈥?Read: 40mA max. (SRAM chip)
鈥?Stand-by: 30碌A(chǔ) max. (SRAM chip)
鈥?Read: 10mA max. (Flash chip)
鈥?Stand-by: 100碌A(chǔ) max. (Flash chip)
LBGA48 (ZM)
6 x 8 solder balls
LGA48 (ZN)
6 x 8 solder lands
BGA
LGA
FLASH MEMORY
s
8 Mbit (1Mb x 8) BOOT BLOCK ERASE
s
s
PROGRAMMING TIME: 10碌s typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
鈥?Program Byte-by-Byte
鈥?Status Register bits and Ready/Busy Output
Figure 1. Logic Diagram
s
s
s
SECURITY PROTECTION MEMORY AREA
INSTRUCTION ADDRESS CODING: 3 digits
MEMORY BLOCKS
鈥?Boot Block (Top or Bottom location)
鈥?Parameter and Main Blocks
20
A0-A19
W
EF
G
RP
E1S
E2S
M36W108AT
M36W108AB
RB
8
DQ0-DQ7
VCCF VCCS
s
s
BLOCK, MULTI-BLOCK and CHIP ERASE
ERASE SUSPEND and RESUME MODES
鈥?Read and Program another Block during
Erase Suspend
s
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
鈥?Manufacturer Code: 20h
鈥?Device Code, M36W108AT: D2h
鈥?Device Code, M36W108AB: DCh
s
SRAM
s
1 Mbit (128Kb x 8)
s
VSS
AI02620
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
LOW V
CC
DATA RETENTION: 2V
1/36
s
March 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.