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M36LLR8760D Datasheet

  • M36LLR8760D

  • 256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Mem...

  • 19頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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M36LLR8760T1, M36LLR8760D1
M36LLR8760M1, M36LLR8760B1
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
TARGET SPECIFICATION
FEATURES SUMMARY
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
MULTI-CHIP PACKAGE
鈥?1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
鈥?1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-Level, Burst) Flash Memory
鈥?1 die of 64 Mbit (4Mb x16) Pseudo SRAM
SUPPLY VOLTAGE
鈥?V
DDF1
= V
DDF2
= V
CCP
= V
DDQF
= 1.7 to
1.95V
鈥?V
PPF
= 9V for fast program (12V tolerant)
ELECTRONIC SIGNATURE
鈥?Manufacturer Code: 20h
鈥?Top Configuration (Top + Top)
M36LLR8760T1: 880Dh + 88C4h
鈥?Mixed Configuration (Bottom + Top)
M36LLR8760D1: 880Eh + 88C4h
鈥?Mixed Configuration (Top + Bottom)
M36LLR8760M1: 880Dh + 88C5h
鈥?Bottom Configuration (Bottom + Bottom)
M36LLR8760B1: 880Eh + 88C5h
PACKAGE
鈥?Compliant with Lead-Free Soldering
Processes
鈥?Lead-Free Versions
Figure 1. Package
FBGA
LFBGA88 (ZAQ)
8 x 10mm
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
FLASH MEMORIES
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
SYNCHRONOUS / ASYNCHRONOUS READ
鈥?Synchronous Burst Read mode: 54MHz
鈥?Asynchronous Page Read mode
鈥?Random Access: 85ns
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
鈥?10碌s typical Word program time using
Buffer Enhanced Factory Program
command
MEMORY ORGANIZATION
鈥?Multiple Bank Memory Array:
16 Mbit Banks for the 256 Mbit Memory
8 Mbit Banks for the 128 Mbit Memory
鈥?Parameter Blocks (at Top or Bottom)
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
DUAL OPERATIONS
鈥?program/erase in one Bank while read in
others
鈥?No delay between read and write
operations
SECURITY
鈥?64 bit unique device number
鈥?2112 bit user programmable OTP Cells
BLOCK LOCKING
鈥?All blocks locked at power-up
鈥?Any combination of blocks can be locked
with zero latency
鈥?WP
F
for Block Lock-Down
鈥?Absolute Write Protection with V
PPF
= V
SS
PSRAM
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
ACCESS TIME: 70ns
ASYNCHRONOUS PAGE READ
鈥?Page Size: 16 words
鈥?Subsequent read within page: 20ns
LOW POWER FEATURES
鈥?Temperature Compensated Refresh
(TCR)
鈥?Partial Array Refresh (PAR)
鈥?Deep Power-Down (DPD) Mode
SYNCHRONOUS BURST READ/WRITE
1/19
July 2005
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.

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