M36DR432ADZA Datasheet

IC型號：
M36DR432ADZA
PDF描述：
32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256...
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52頁
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STMICROELECTRONICS

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M36DR432AD

M36DR432BD

32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory

and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product

FEATURES SUMMARY

Multiple Memory Product

鈥?1 bank of 32 Mbit (2Mb x16) Flash Memory

鈥?1 bank of 4 Mbit (256Kb x16) SRAM

SUPPLY VOLTAGE

鈥?V

DDF

= V

DDS

=1.65V to 2.2V

鈥?V

PPF

= 12V for Fast Program (optional)

Figure 1. Package

ACCESS TIMES: 85ns, 100ns, 120ns

LOW POWER CONSUMPTION

ELECTRONIC SIGNATURE

鈥?Manufacturer Code: 0020h

鈥?Top Device Code, M36DR432AD: 00A0h

鈥?Bottom Device Code, M36DR432BD: 00A1h

FBGA

Stacked LFBGA66 (ZA)

12 x8mm

FLASH MEMORY

MEMORY BLOCKS

鈥?Dual Bank Memory Array: 4 Mbit, 28 Mbit

鈥?Parameter Blocks (Top or Bottom location)

PROGRAMMING TIME

鈥?10碌s by Word typical

鈥?Double Word Program Option

ERASE SUSPEND and RESUME MODES

100,000 PROGRAM/ERASE CYCLES per

BLOCK

20 YEARS DATA RETENTION

鈥?Defectivity below 1ppm/year

ASYNCHRONOUS PAGE MODE READ

鈥?Page Width: 4 Words

鈥?Page Access: 35ns

鈥?Random Access: 85ns, 100ns, 120ns

DUAL BANK OPERATIONS

鈥?Read within one Bank while Program or

Erase within the other

鈥?No delay between Read and Write operations

SRAM

4 Mbit (256Kb x16)

LOW V

DDS

DATA RETENTION: 1.0V

POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

BLOCK LOCKING

鈥?All blocks locked at Power up

鈥?Any combination of blocks can be locked

鈥?WPF for Block Lock-Down

COMMON FLASH INTERFACE (CFI)

鈥?64 bit Unique Device Identifier

鈥?64 bit User Programmable OTP Cells

February 2003

1/52

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M36DR432ADZA Datasheet

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